METHOD FOR DESIGNING INTEGRATED CIRCUITS COMPRISING REPLACEMENT LOGIC GATES
    1.
    发明申请
    METHOD FOR DESIGNING INTEGRATED CIRCUITS COMPRISING REPLACEMENT LOGIC GATES 审中-公开
    方法集成电路与替换逻辑GATES设计

    公开(公告)号:WO2005022629A3

    公开(公告)日:2005-04-21

    申请号:PCT/DE2004001825

    申请日:2004-08-16

    CPC classification number: G06F17/5068

    Abstract: The invention relates to a method for designing integrated circuits that comprise replacement logic chips. According to said method, a plurality of logic cells and a plurality of filler cells for filling the gaps between the logic cells is placed on a chip surface. Some or all of the filler cells represent replacement logic chips for the integrated circuit and are interconnected or wired in such a manner as to form capacitors (2, 3) in the integrated circuit.

    Abstract translation: 在设计集成电路与备用逻辑器件的方法中,多个逻辑单元和多个填料单元,所述填充逻辑单元之间的空间,放置在芯片表面。 在这种情况下代表的一些或全部填充单元更换逻辑的用于集成电路和是,或者是这样的有线或有线的,与电容器(2,3)在所述集成电路形成。

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