公开(公告)号：WO2005008774A3

公开(公告)日：2005-08-11

申请号：PCT/DE2004001365

申请日：2004-06-29

Applicant: INFINEON TECHNOLOGIES AG ,  ENGL KORBINIAN ,  SEDLAK HOLGER ,  SIMONS PETER ,  UFFMANN DIRK

Inventor： ENGL KORBINIAN ,  SEDLAK HOLGER ,  SIMONS PETER ,  UFFMANN DIRK

IPC: H01L23/48 ,  H01L23/50 ,  H01L23/60 ,  H01L23/62

CPC classification number: H01L23/60 ,  H01L24/06 ,  H01L24/49 ,  H01L2224/05554 ,  H01L2224/49171 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01068 ,  H01L2924/14 ,  H01L2924/00 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

Abstract: Disclosed is a semiconductor chip in which the terminal contact areas (1) and a strip conductor (2) providing ESD protection are grouped together in a narrowly confined zone (3) by passing the contact wires (4) to additional terminal contact areas (5) of a housing via at least two edges of the chip so as to save on the surface required.

Abstract translation: 端子接触表面（1）和提供用于ESD保护导体（2）被分组以面对保存在狭窄的区域（3）中，当键合线（4）的另一端的接触表面（5）的壳体在芯片的至少两个边缘的 引导。

公开(公告)号：DE10331570A1

公开(公告)日：2005-02-17

申请号：DE10331570

申请日：2003-07-11

Applicant: INFINEON TECHNOLOGIES AG

Inventor： SEDLAK HOLGER ,  ENGL KORBINIAN ,  SIMONS PETER ,  UFFMANN DIRK

IPC: H01L23/48 ,  H01L23/50 ,  H01L23/60 ,  H01L23/62

Abstract: Disclosed is a semiconductor chip in which the terminal contact areas (1) and a strip conductor (2) providing ESD protection are grouped together in a narrowly confined zone (3) by passing the contact wires (4) to additional terminal contact areas (5) of a housing via at least two edges of the chip so as to save on the surface required.

公开(公告)号：DE10331570B4

公开(公告)日：2005-09-22

申请号：DE10331570

申请日：2003-07-11

Applicant: INFINEON TECHNOLOGIES AG

Inventor： SEDLAK HOLGER ,  ENGL KORBINIAN ,  SIMONS PETER ,  UFFMANN DIRK

IPC: H01L23/48 ,  H01L23/50 ,  H01L23/60 ,  H01L23/62

Abstract: Disclosed is a semiconductor chip in which the terminal contact areas (1) and a strip conductor (2) providing ESD protection are grouped together in a narrowly confined zone (3) by passing the contact wires (4) to additional terminal contact areas (5) of a housing via at least two edges of the chip so as to save on the surface required.

公开(公告)号：DE10337418A1

公开(公告)日：2004-09-23

申请号：DE10337418

申请日：2003-08-14

Applicant: INFINEON TECHNOLOGIES AG

Inventor： SEDLAK HOLGER ,  WEDER UWE ,  GEHLE MARCUS ,  ENGL KORBINIAN ,  SIMONS PETER

IPC: H03K5/04 ,  H03K5/06 ,  H03K5/156

Abstract: The integrated digital circuit has a functional part (7) receiving a clock signal with a defined duty cycle, a clock signal generator (8) and a controllable duty cycle change device (2) that forwards the clock signal with altered duty cycle to the functional part, whereby the duty cycle is changed in accordance with a signal applied to the control input (4) of the duty cycle change device.