公开(公告)号：DE10244186B4

公开(公告)日：2008-03-06

申请号：DE10244186

申请日：2002-09-23

Applicant: INFINEON TECHNOLOGIES AG

Inventor： TAGHIZADEH-KASCHANI KARIM-THOM

IPC: H04L25/20 ,  H03K5/08 ,  H04L25/02

Abstract: A receiver circuit for push-pull transmission has at least first and second inputs (E1,E2) for supplying first and second input signals (In1, In2) and providing an output signal (Out) therefrom. A detector circuit (10A) has first and second detectors (11,12) for comparing the amplitude of each respective input signal (In1;In2) with a detection threshold, and for preparing detector output signals (CLK1,CLK2). Each signal detector has a control input for adjusting the detector threshold. A signal processing circuit (20) receives the detector output signals and provides an output signal (Out) according to the value of the detector output signals (CLK1,CLK2). The signal processing circuit (20) specifically includes a signal flank 'spacing/distance' evaluation unit for detecting specified flanks of the detector output signals and preparing output signals. An Independent claim is included for a method for detecting first and second signals during push-pull transmission.

公开(公告)号：DE10357495A1

公开(公告)日：2005-07-14

申请号：DE10357495

申请日：2003-12-09

Applicant: INFINEON TECHNOLOGIES AG

Inventor： TAGHIZADEH-KASCHANI KARIM-THOM

IPC: H03K3/012 ,  H03K3/356 ,  H03K17/10 ,  H03K19/0185 ,  H03K19/017

Abstract: A level converter comprises a signal input (K1) a level converter with two output transistors (M3,M4) and switching nodes (N1,N2) and a second level converter having two capacitors (C1,C2) coupled to the nodes and a level detector (10) with two inputs (11,12) and producing at least one output signal (Sout).

公开(公告)号：DE19944519A1

公开(公告)日：2001-03-22

申请号：DE19944519

申请日：1999-09-16

Applicant: INFINEON TECHNOLOGIES AG

Inventor： TAGHIZADEH-KASCHANI KARIM-THOM

IPC: H03K17/0412 ,  H03K17/16 ,  H03K19/003 ,  H03K17/042 ,  H03F3/217 ,  H03K17/687

Abstract: The invention relates to a circuit arrangement alternating connection of a load to a high and low supply potential according to a control signal supplied to an input. The inventive circuit arrangement has a first push-pull output stage consisting of a first and second semi-conductor switch. Said output stage is switched between a first and a second supply potential connection. A load is connected to a connection point of a first and second semi-conductor switch. A second push-pull stage consisting of a third and a fourth semi-conductor switch is also provided,. Said switches are mounted between a first and a second supply potential connection, whereby a semi-conducting switch of the second of the second push-pull output stage only conducts when a semi-conductor switch of the first push-pull output stage is blocked. A power-semi-conductor switch is intended to act as a load. Said semiconductor switch which forms the base element of a synchronized electrical supply in conjunction with a transformer coil.

公开(公告)号：DE10357495B4

公开(公告)日：2005-11-10

申请号：DE10357495

申请日：2003-12-09

Applicant: INFINEON TECHNOLOGIES AG

Inventor： TAGHIZADEH-KASCHANI KARIM-THOM

IPC: H03K3/012 ,  H03K3/356 ,  H03K17/10 ,  H03K19/0185 ,  H03K19/017

公开(公告)号：DE10216605A1

公开(公告)日：2003-10-30

申请号：DE10216605

申请日：2002-04-15

Applicant: INFINEON TECHNOLOGIES AG

Inventor： TAGHIZADEH-KASCHANI KARIM-THOM

IPC: H03M9/00 ,  H04L25/28 ,  H04L25/49

Abstract: Data, e.g. an eight-bit word (DW) is input to two parallel circuits. The first circuit adds two initialization data bits (IB) and includes a parallel-series converter. It outputs and transmits a first set of data signals (TData). The second circuit has a differentiating or inverting stage producing the differential or inverse of the eight-bit word (IDW). There is an initialization bit adding circuit and a parallel-series converter. It outputs a second set of signals (/TData). A clock is connected to the parallel-series converters.

公开(公告)号：DE50308264D1

公开(公告)日：2007-11-08

申请号：DE50308264

申请日：2003-05-30

Applicant: INFINEON TECHNOLOGIES AG

Inventor： TAGHIZADEH-KASCHANI KARIM-THOM

IPC: H04L25/08 ,  H04L1/22

Abstract: A signal (Sin) is input to a transmitter circuit (1) which produces a train of pulses (PS). A channel signal (KS) may be detected and may be fed back to the transmitter. The transmission line (3) may be subjected to interference (Storung) and is connected to inductively coupled windings (GND1,GND2) which may be connected to different potentials. The modified signal is passed to a receiver (2) which produces an output signal (Sout).

公开(公告)号：DE10228543A1

公开(公告)日：2005-11-03

申请号：DE10228543

申请日：2002-06-26

Applicant: INFINEON TECHNOLOGIES AG

Inventor： STRZALKOWSKI BERNHARD ,  TAGHIZADEH-KASCHANI KARIM-THOM

IPC: H04L25/08 ,  H04L25/20 ,  H04L25/49

Abstract: The method involves releasing an impulse sequence (Spos, Sneg) with temporally distanced impulses to a channel, after change of a signal level. The temporal distance in each successive impulses of the sequence is uneven. The temporal distance increases with increase in temporal distance to the changes of the signal level. The temporal distance varies randomly or pseudo-randomly. An independent claim is also included for a transmission device to transmit information in a bivalent signal over a channel.

公开(公告)号：DE10202480A1

公开(公告)日：2002-08-14

申请号：DE10202480

申请日：2002-01-23

Applicant: INFINEON TECHNOLOGIES AG

Inventor： STENGL JENS-PEER ,  TAGHIZADEH-KASCHANI KARIM-THOM ,  TIHANYI JENOE ,  WERNER WOLFGANG

IPC: H03K17/06 ,  H03K17/567 ,  H03K17/689 ,  H04B1/20 ,  G08C17/02

Abstract: A signal to be transferred between electronic modules (3,4,7,8), is converted into a line-independent electromagnetic wave by respective transmitters (31,41,71,81) and outputs to receivers (32,42,72,82). The electromagnetic wave is converted into a reception signal using receivers at the receiving electronic module. An independent claim is included for system for transferring signals between two electronic modules.

公开(公告)号：DE102004014752A1

公开(公告)日：2005-11-03

申请号：DE102004014752

申请日：2004-03-25

Applicant: INFINEON TECHNOLOGIES AG

Inventor： TAGHIZADEH-KASCHANI KARIM-THOM

IPC: H01F17/00 ,  H01F27/28 ,  H01L21/4763 ,  H01L23/48 ,  H01L23/52 ,  H01L23/522 ,  H01L23/58 ,  H01L27/01

Abstract: The invention relates to a semiconductor component having a coreless first transformer ( 71, 72 ) which comprises a first ( 71 ) and a second ( 72 ) planar winding, is arranged on a semiconductor body 9 and is surrounded in the lateral direction by a protective ring ( 1, 2 ). The protective ring ( 1, 2 ) has metal portions ( 1 a- 1 d), of which the top metal portion ( 1 a) is further apart of the first planar winding ( 71 ) in the lateral direction than the protective ring ( 1 b) which is second from top.

公开(公告)号：DE102004013093B3

公开(公告)日：2005-07-21

申请号：DE102004013093

申请日：2004-03-17

Applicant: INFINEON TECHNOLOGIES AG

Inventor： TAGHIZADEH-KASCHANI KARIM-THOM ,  MARTINEZ JOSE-MARIA

IPC: H01J40/14 ,  H04L25/02 ,  H04L25/08 ,  H04L25/14 ,  H04L25/40

Abstract: The receiver circuit has first and second inputs (IN1,IN2) for first and second input signals (Sin1,Sin2), first and second signal detectors (11,21) for the first input signal, third and fourth signal detectors (12,22) for the second input signal, first and second temporary memories (51,52) and a combination circuit (60) for generating an output signal (Sout) depending on the output signals of the temporary memories.