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    Semiconductor device
    1.
    发明专利
    Semiconductor device 审中-公开
    半导体器件

    公开(公告)号：JP2006093451A

    公开(公告)日：2006-04-06

    申请号：JP2004278030

    申请日：2004-09-24

    Applicant: Infineon Technologies Ag ,  Toshiba Corp ,  インフィネオン テクノロジース アクチエンゲゼルシャフト ,  株式会社東芝

    Inventor： TOMIOKA KAZUHIRO ,  ISHIDA TOMOAKI ,  FUKUSHIMA MASATOSHI ,  BABA MASANOBU ,  KANETANI HIROYUKI ,  ZHUANG HAOREN

    IPC: H01L27/105 ,  H01L21/8246

    CPC classification number: H01L28/65 ,  H01L21/0334 ,  H01L21/31122 ,  H01L21/31144 ,  H01L21/32136 ,  H01L21/32139 ,  H01L28/55

    Abstract: PROBLEM TO BE SOLVED: To provide a semiconductor device which is made superior in a characteristic and reliability by optimizing the inclination of the side face of a capacitor.
    SOLUTION: This semiconductor device comprises a capacitor which contains a semiconductor substrate 10; a lower electrode 21 provided on the upper side of the semiconductor substrate, a dielectric film 22 provided on the lower electrode, and an upper electrode 23 provided on the dielectric film; and a mask film 31 which is provided on the upper electrode, and is used as a mask when the pattern of the capacitor is formed. The inclination of the side face of the mask film is gentler than the inclination of the side face of the upper electrode and the inclination of the side face of the dielectric film.
    COPYRIGHT: (C)2006,JPO&NCIPI

    Abstract translation: 要解决的问题：通过优化电容器的侧面的倾斜来提供通过优化特性和可靠性的半导体器件。 解决方案：该半导体器件包括含有半导体衬底10的电容器; 设置在半导体衬底的上侧的下电极21，设置在下电极上的电介质膜22和设置在电介质膜上的上电极23; 以及设置在上电极上的掩模膜31，并且当形成电容器的图案时用作掩模。 掩模膜的侧面的倾斜度比上电极的侧面的倾斜度和电介质膜的侧面的倾斜度更平缓。 版权所有（C）2006，JPO＆NCIPI

    Measurement system and method for lithography process
    2.
    发明专利
    Measurement system and method for lithography process 有权
    测量过程的测量系统和方法

    公开(公告)号：JP2008096973A

    公开(公告)日：2008-04-24

    申请号：JP2007211402

    申请日：2007-08-14

    Applicant: Infineon Technologies Ag ,  インフィネオン テクノロジーズ アクチエンゲゼルシャフト

    Inventor： LIAN JINGYU ,  LIPINSKY MATTHIAS ,  SARMA CHANDRASEKHAR ,  ZHUANG HAOREN

    IPC: G03F1/08 ,  H01L21/027

    CPC classification number: G03F7/70425 ,  G03F7/70483

    Abstract: PROBLEM TO BE SOLVED: To provide: a measurement system by which corner rounding is reduced; a measurement method; an alteration of a mask; and a lithography process. SOLUTION: A method of manufacturing a semiconductor device includes providing a mask having a plurality of corner rounding test patterns formed thereon. A layer of photosensitive material of a first semiconductor device is patterned with a plurality of corner rounding test features using the mask and a lithography process. An amount of the corner rounding of the lithography process is measured by analyzing the plurality of corner rounding test features formed on the layer of photosensitive material of the semiconductor device, compared with a plurality of other corner rounding test features. The lithography process or the mask is altered in response to the amount of corner rounding measured, and a second semiconductor device is provided. The second semiconductor device is processed using the altered lithography process or the altered mask. COPYRIGHT: (C)2008,JPO&INPIT

    Abstract translation: 要解决的问题：提供：减少角落圆度的测量系统; 测量方法; 改变面具; 和光刻工艺。 解决方案：制造半导体器件的方法包括提供具有形成在其上的多个角圆形测试图案的掩模。 使用掩模和光刻工艺，利用多个拐角圆形测试特征对第一半导体器件的感光材料层进行构图。 通过分析形成在半导体器件的感光材料层上的多个拐角圆形测试特征，与多个其他圆角圆形测试特征相比，测量光刻工艺的角圆角的量。 光刻处理或掩模响应于测量的角圆度的量而改变，并且提供第二半导体器件。 使用改变的光刻工艺或改变的掩模来处理第二半导体器件。 版权所有（C）2008，JPO＆INPIT

    4.
    发明专利
    未知

    公开(公告)号：DE112004001776T5

    公开(公告)日：2006-08-24

    申请号：DE112004001776

    申请日：2004-08-31

    Applicant: INFINEON TECHNOLOGIES AG

    Inventor： ZHUANG HAOREN ,  EGGER ULRICH

    IPC: H01L21/20 ,  H01L21/02 ,  H01L21/033 ,  H01L21/311 ,  H01L21/3213

    Abstract: A ferroelectric capacitor device, such as an FeRAM device is formed by forming a substrate extending in a first plane and comprising a number of layers of material, forming a hard mask layer on the substrate and forming a first layer of a first material on the hard mask layer. The hard mask shape is then defined by etching the hard mask layer. A second layer of the first material is deposited on the etched hard mask layer. The deposited second layer has one or more side surfaces extending substantially perpendicular to the plane of the substrate. The second layer and the number of layers forming the substrate are then etched to shape the ferroelectric capacitor device.

    A METHOD OF ETCHING FERROELECTRIC DEVICES
    6.
    发明申请
    A METHOD OF ETCHING FERROELECTRIC DEVICES 审中-公开
    一种蚀刻电介质器件的方法

    公开(公告)号：WO2004077541A2

    公开(公告)日：2004-09-10

    申请号：PCT/SG2004000034

    申请日：2004-02-09

    Applicant: INFINEON TECHNOLOGIES AG ,  EGGER ULRICH ,  ZHUANG HAOREN ,  BRUCHHAUS RAINER

    Inventor： EGGER ULRICH ,  ZHUANG HAOREN ,  BRUCHHAUS RAINER

    IPC: H01L21/02 ,  H01L21/311 ,  H01L21/3213

    CPC classification number: H01L21/32139 ,  H01L21/31122 ,  H01L21/32136 ,  H01L28/55 ,  H01L28/60

    Abstract: A method of etching a ferroelectric device (100) having a ferroelectric layer (112) between a top and a bottom electrode (114, 108) is disclosed herein. Hardmasks (116, 118) are deposited on the top electrode (114), two or more hardmasks being spaced apart by narrow first regions (115) and spaced apart from other hardmasks by wider second regions (117). The top electrode (114) and ferroelectric layer (112) are then etched to pattern the top electrode (114) thus forming capacitors (102, 104), and the bottom electrode (108) is etched by a process in which the second regions are etched more slowly than the second regions. Those capacitors having a first region between them have a common bottom electrode (108), but in the second regions the bottom electrode is severed. To pattern the bottom electrode (108), a fluorine-based chemistry followed thereafter by a CO-based chemistry are used in a two step etching process.

    Abstract translation: 本文公开了一种在顶部电极和底部电极（114,108）之间蚀刻具有铁电体层（112）的铁电体元件（100）的方法。 硬掩模（116,118）沉积在顶部电极（114）上，两个或更多个硬掩模由窄的第一区域（115）间隔开，并且由较宽的第二区域（117）与其它硬掩模隔开。 然后蚀刻顶部电极（114）和铁电体层（112）以对顶部电极（114）进行图案，从而形成电容器（102,104），并且通过其中第二区域 蚀刻比第二区域更缓慢。 那些在它们之间具有第一区域的电容器具有共同的底部电极（108），但是在第二区域中，底部电极被切断。 为了对底部电极（108）进行图案化，其后采用基于CO的化学物质的氟基化学物质用于两步蚀刻工艺。

    FERROELECTRIC CAPACITOR AND PROCESS FOR ITS MANUFACTURE
    7.
    发明申请
    FERROELECTRIC CAPACITOR AND PROCESS FOR ITS MANUFACTURE 审中-公开
    铁电电容器及其制造工艺

    公开(公告)号：WO2004051711A3

    公开(公告)日：2004-08-26

    申请号：PCT/SG0300271

    申请日：2003-11-17

    Applicant: INFINEON TECHNOLOGIES AG ,  EGGER ULRICH ,  ZHUANG HAOREN ,  HORNIK KARL

    Inventor： EGGER ULRICH ,  ZHUANG HAOREN ,  HORNIK KARL

    IPC: H01L21/02 ,  H01L21/311 ,  H01L21/316 ,  H01L21/8246 ,  H01L27/10 ,  H01L27/115

    CPC classification number: H01L28/55 ,  H01L21/02178 ,  H01L21/02266 ,  H01L21/31116 ,  H01L21/3162

    Abstract: A method of forming a capacitor, comprises the steps of (a) forming a matrix of ferroelectric capacitor elements on a substrate, (b) forming a CAP layer over the ferroelectric capacitor elements, and (c) etching the CAP layer to a more uniform thickness. Also, a capacitor comprises a substrate layer, a matrix of ferroelectric capacitor elements including a first electrode layer substantially fixed relative to the substrate, a second electrode layer, and a ferroelectric layer sandwiched between the first and second electrode layers; a shoulder layer extending from the substrate to the matrix; and a CAP layer etched to have substantially constant thickness covering sides of the matrix extending beyond the substrate.

    Abstract translation: 一种形成电容器的方法，包括以下步骤：（a）在衬底上形成铁电电容器元件的矩阵，（b）在铁电电容器元件上形成CAP层，以及（c）将CAP层蚀刻到更均匀 厚度。 此外，电容器包括衬底层，铁电电容器元件矩阵，包括相对于衬底基本上固定的第一电极层，第二电极层和夹在第一和第二电极层之间的铁电层; 从衬底延伸到基体的肩层; 以及被蚀刻以具有基本上恒定厚度的CAP层，覆盖延伸超过衬底的基体的侧面。

    METHOD OF PATTERNING CAPACITORS AND CAPACITORS MADE THEREBY
    8.
    发明申请
    METHOD OF PATTERNING CAPACITORS AND CAPACITORS MADE THEREBY 审中-公开
    绘制电容器和电容器的方法

    公开(公告)号：WO2004030069A3

    公开(公告)日：2004-06-10

    申请号：PCT/SG0300220

    申请日：2003-09-17

    Applicant: INFINEON TECHNOLOGIES AG

    Inventor： LIAN JENNY ,  ZHUANG HAOREN ,  EGGER ULRICH ,  HORNIK KARL

    IPC: H01L21/02 ,  H01L21/311

    CPC classification number: H01L28/55 ,  H01L21/31122

    Abstract: A method of forming a ferroelectric capacitor, in particular for use in a FeRAM or high-k DRAM application, and a capacitor made by the method. The method comprises forming a first layer which is patterned, for example by a reactive ion etching method. A ferroelectric material is then formed over the patterned first layer. The morphology of the ferroelectric material will be dependent upon the patterning of the first layer. The ferroelectric layer is then patterned, for example using a wet etching or a reactive ion etching method. The etching will depend upon the morphology of the ferroelectric layer. After etching the ferroelectric layer, a conductive layer is provided over the ferroelectric layer to form a first electrode of the capacitor. If the first layer is a conductive layer, this forms the second electrode. If the first layer is a non-conductive layer,. the conductive layer is patterned to form both the first and second electrodes.

    Abstract translation: 形成铁电电容器的方法，特别是用于FeRAM或高k DRAM应用的方法，以及由该方法制成的电容器。 该方法包括形成图案化的第一层，例如通过反应离子蚀刻方法。 然后在图案化的第一层上形成铁电材料。 铁电材料的形态将取决于第一层的图案化。 然后将铁电层图案化，例如使用湿式蚀刻或反应离子蚀刻方法。 蚀刻将取决于铁电层的形态。 在对铁电体层进行蚀刻之后，在铁电层上设置导电层，形成电容器的第一电极。 如果第一层是导电层，则形成第二电极。 如果第一层是非导电层， 图案化导电层以形成第一和第二电极。

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