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    METHOD OF PATTERNING CAPACITORS AND CAPACITORS MADE THEREBY
    1.
    发明申请
    METHOD OF PATTERNING CAPACITORS AND CAPACITORS MADE THEREBY 审中-公开
    绘制电容器和电容器的方法

    公开(公告)号：WO2004030069A3

    公开(公告)日：2004-06-10

    申请号：PCT/SG0300220

    申请日：2003-09-17

    Applicant: INFINEON TECHNOLOGIES AG

    Inventor： LIAN JENNY ,  ZHUANG HAOREN ,  EGGER ULRICH ,  HORNIK KARL

    IPC: H01L21/02 ,  H01L21/311

    CPC classification number: H01L28/55 ,  H01L21/31122

    Abstract: A method of forming a ferroelectric capacitor, in particular for use in a FeRAM or high-k DRAM application, and a capacitor made by the method. The method comprises forming a first layer which is patterned, for example by a reactive ion etching method. A ferroelectric material is then formed over the patterned first layer. The morphology of the ferroelectric material will be dependent upon the patterning of the first layer. The ferroelectric layer is then patterned, for example using a wet etching or a reactive ion etching method. The etching will depend upon the morphology of the ferroelectric layer. After etching the ferroelectric layer, a conductive layer is provided over the ferroelectric layer to form a first electrode of the capacitor. If the first layer is a conductive layer, this forms the second electrode. If the first layer is a non-conductive layer,. the conductive layer is patterned to form both the first and second electrodes.

    Abstract translation: 形成铁电电容器的方法，特别是用于FeRAM或高k DRAM应用的方法，以及由该方法制成的电容器。 该方法包括形成图案化的第一层，例如通过反应离子蚀刻方法。 然后在图案化的第一层上形成铁电材料。 铁电材料的形态将取决于第一层的图案化。 然后将铁电层图案化，例如使用湿式蚀刻或反应离子蚀刻方法。 蚀刻将取决于铁电层的形态。 在对铁电体层进行蚀刻之后，在铁电层上设置导电层，形成电容器的第一电极。 如果第一层是导电层，则形成第二电极。 如果第一层是非导电层， 图案化导电层以形成第一和第二电极。

    3.
    发明专利
    未知

    公开(公告)号：DE10356097B4

    公开(公告)日：2008-01-31

    申请号：DE10356097

    申请日：2003-11-27

    Applicant: INFINEON TECHNOLOGIES AG

    Inventor： WELLHAUSEN UWE ,  BRUCHHAUS RAINER ,  NAGEL NICOLAS ,  GERNHARDT STEFAN ,  LIAN JENNY ,  HILLINGER ANDREAS

    IPC: H01L21/283 ,  H01L21/02 ,  H01L21/768 ,  H01L21/8239 ,  H01L23/48

    Abstract: The invention includes a wafer having a poly silicon plug passing through a CP-contact. The poly silicon plug is formed from a relatively heavily doped poly silicon layer and a relatively lightly doped poly silicon layer. The relatively lightly doped poly silicon layer passes through the relatively heavily doped poly silicon layer to extend beyond the relatively heavily doped poly silicon layer towards the surface of the wafer. A barrier layer covers top and side walls of the relatively lightly doped poly silicon layer for reducing oxidation at the surface of the poly silicon plug. The wafer is fabricated by depositing a relatively heavily doped poly silicon layer in a CP-contact, depositing a relatively lightly doped poly silicon layer to pass through the relatively heavily doped poly silicon layer, and depositing a barrier layer to cover top and side walls of the relatively lightly doped poly silicon layer to reduce oxidation at the surface of the poly silicon plug.

    4.
    发明专利
    未知

    公开(公告)号：DE10356097A1

    公开(公告)日：2004-06-17

    申请号：DE10356097

    申请日：2003-11-27

    Applicant: INFINEON TECHNOLOGIES AG

    Inventor： WELLHAUSEN UWE ,  BRUCHHAUS RAINER ,  NAGEL NICOLAS ,  GERNHARDT STEFAN ,  LIAN JENNY ,  HILLIGER ANDREAS

    IPC: H01L21/02 ,  H01L21/768 ,  H01L27/105 ,  H01L21/8239

    Abstract: The invention includes a wafer having a poly silicon plug passing through a CP-contact. The poly silicon plug is formed from a relatively heavily doped poly silicon layer and a relatively lightly doped poly silicon layer. The relatively lightly doped poly silicon layer passes through the relatively heavily doped poly silicon layer to extend beyond the relatively heavily doped poly silicon layer towards the surface of the wafer. A barrier layer covers top and side walls of the relatively lightly doped poly silicon layer for reducing oxidation at the surface of the poly silicon plug. The wafer is fabricated by depositing a relatively heavily doped poly silicon layer in a CP-contact, depositing a relatively lightly doped poly silicon layer to pass through the relatively heavily doped poly silicon layer, and depositing a barrier layer to cover top and side walls of the relatively lightly doped poly silicon layer to reduce oxidation at the surface of the poly silicon plug.

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