公开(公告)号：DE10305729A1

公开(公告)日：2003-08-28

申请号：DE10305729

申请日：2003-02-12

Applicant: INFINEON TECHNOLOGIES AG ,  IBM

Inventor： CHAKRAVARTI ASHIMA B ,  GLUSCHENKOV OLEG ,  MCSTAY IRENE

IPC: C23C16/04 ,  C23C16/44 ,  C23C16/455 ,  C23C16/48 ,  C23C16/52 ,  H01L21/00 ,  H01L21/316 ,  H01L21/318 ,  H01L21/8242 ,  H01L21/3205 ,  H01L21/324

Abstract: An apparatus (110) and method for depositing material on a semiconductor wafer with non-planar structures (114). The wafer (114) is positioned in a chamber (111), and reactive gases (132) are introduced into the chamber (111). The gases (132) and wafer (114) are heated, wherein the gas (132) temperature in the process chamber (111) and in the vicinity of the wafer (114) surface is lower than the temperature of the wafer (114) surface. A material is deposited on the wafer (114) surface using chemical vapor deposition. A gas cooler may be utilized to lower the temperature of the reactive gases (132) while the wafer (114) is heated.

公开(公告)号：EP2050128A4

公开(公告)日：2009-12-23

申请号：EP07813250

申请日：2007-07-24

Applicant: IBM

Inventor： CHAKRAVARTI ASHIMA B ,  CHIDAMBARRAO DURESETI ,  HOLT JUDSON R ,  LIU YAOCHENG ,  RIM KERN

IPC: H01L21/336 ,  H01L21/762 ,  H01L21/8238

CPC classification number: H01L21/823864 ,  H01L21/76224 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/823878 ,  H01L29/165 ,  H01L29/66628 ,  H01L29/7843 ,  H01L29/7848

公开(公告)号：JP2007081361A

公开(公告)日：2007-03-29

申请号：JP2006001706

申请日：2006-01-06

Applicant: Internatl Business Mach Corp ,  インターナショナル・ビジネス・マシーンズ・コーポレーションInternational Business Maschines Corporation

Inventor： CHAKRAVARTI ASHIMA B ,  CHOU ANTHONY I ,  FURUKAWA TOSHIHARU ,  STEVEN J HOLMES ,  NATZLE WESLEY C

IPC: H01L21/205 ,  H01L21/3065 ,  H01L29/78

CPC classification number: H01L29/7833 ,  H01L21/02532 ,  H01L21/02587 ,  H01L21/0262 ,  H01L21/02639 ,  H01L29/665 ,  H01L29/6653 ,  H01L29/6656 ,  H01L29/6659 ,  H01L2224/05571 ,  H01L2224/05573 ,  H01L2224/10126 ,  H01L2224/13023 ,  H01L2924/1305 ,  H01L2924/00

Abstract: PROBLEM TO BE SOLVED: To provide a structure and a method for selectively accumulating a germanium spacer on a nitride. SOLUTION: In a method for selectively forming a germanium structure in a semiconductor manufacturing process, a native oxide is removed in a chemical oxide removing (COR) process, then surfaces of heated nitride and oxide are exposed to a germanium-containing gas to selectively form the germanium only on the surface of the nitride, not on the surface of the oxide. COPYRIGHT: (C)2007,JPO&INPIT

Abstract translation: 要解决的问题：提供一种用于在氮化物上选择性地积聚锗间隔物的结构和方法。 解决方案：在半导体制造工艺中选择性地形成锗结构的方法中，在化学氧化物去除（COR）工艺中除去天然氧化物，然后将加热的氮化物和氧化物的表面暴露于含锗气体 以仅选择性地在氮化物的表面上形成锗，而不是在氧化物的表面上形成锗。 版权所有（C）2007，JPO＆INPIT

公开(公告)号：JP2005217400A

公开(公告)日：2005-08-11

申请号：JP2005011467

申请日：2005-01-19

Applicant: Internatl Business Mach Corp ,  インターナショナル・ビジネス・マシーンズ・コーポレーションInternational Business Maschines Corporation

Inventor： CHAKRAVARTI ASHIMA B ,  DORIS BRUCE B ,  GHALI ROMANY ,  GLUSCHENKOV OLEG G ,  GRIBELYUK MICHAEL A ,  LEE WOO-HYEONG ,  MADAN ANITA

IPC: C23C16/24 ,  C23C16/46 ,  H01L21/00 ,  H01L21/205 ,  H01L21/28 ,  H01L21/285 ,  H01L21/3205 ,  H01L29/423 ,  H01L29/49 ,  H01L29/78

CPC classification number: C23C16/24 ,  C23C16/46 ,  H01L21/28035 ,  H01L21/32055 ,  H01L29/4925

Abstract: PROBLEM TO BE SOLVED: To provide a method of forming a polycrystalline silicon having hyperfine particle sizes.
SOLUTION: The method of forming a polycrystalline silicon having hyperfine particle sizes employs a differential heating of upper and lower surfaces of a substrate of a CVD apparatus, in which the lower surface of the substrate receives considerably more power than the upper surface, preferably more than 75% of the entire power; and in which the substrate is maintained during deposition at a temperature higher than 50°C above 550°C of crystallization temperature of silicon.
COPYRIGHT: (C)2005,JPO&NCIPI

Abstract translation: 待解决的问题：提供一种形成具有超细粒径的多晶硅的方法。 解决方案：形成具有超细粒度的多晶硅的方法采用CVD装置的基板的上表面和下表面的差加热，其中基板的下表面比上表面受到相当大的功率， 优选超过整个功率的75％; 并且其中在高于硅的结晶温度高于550℃的温度高于50℃的温度下沉积时，保持基板。 版权所有（C）2005，JPO＆NCIPI

公开(公告)号：JP2006013503A

公开(公告)日：2006-01-12

申请号：JP2005182180

申请日：2005-06-22

Applicant: Internatl Business Mach Corp ,  インターナショナル・ビジネス・マシーンズ・コーポレーションInternational Business Maschines Corporation

Inventor： CHAKRAVARTI ASHIMA B ,  JUDSON HOLT ,  CHAN KEVIN K ,  DESHPANDE SADANAND V ,  JAGANNATHAN RANGARAJAN

IPC: H01L21/318 ,  C23C16/30 ,  C23C16/34 ,  C23C16/40 ,  H01L21/283 ,  H01L21/314 ,  H01L21/316 ,  H01L21/336 ,  H01L21/768 ,  H01L29/78 ,  H01L29/786

CPC classification number: H01L29/7843 ,  C23C16/308 ,  C23C16/34 ,  C23C16/401 ,  H01L21/0214 ,  H01L21/0217 ,  H01L21/02271 ,  H01L21/3143 ,  H01L21/3144 ,  H01L21/3145 ,  H01L21/3148 ,  H01L21/31608 ,  H01L21/31612 ,  H01L21/3185 ,  H01L21/76801 ,  H01L21/76829 ,  H01L21/76834 ,  H01L29/7833 ,  H01L29/78675

Abstract: PROBLEM TO BE SOLVED: To provide films, especially silicon nitride films, silicon oxide films, silicon oxynitride films, and silicon carbide films, which are formed more easily at a higher deposition rate in comparison with conventional processes.
SOLUTION: Adding at least one non-silicon precursor (such as a germanium precursor and a carbon precursor) during formation of a silicon nitride, silicon oxide, silicon oxynitride or silicon carbide film improves the deposition rate, and/or allows properties, such as the stress, of the film to be adjusted. Also, in a doped silicon oxide or doped silicon nitride or any other doped structure, the presence of a dopant can be used for measuring a signal (marking) associated with the dopant as an etch stop, or in other cases, for achieving control during etching.
COPYRIGHT: (C)2006,JPO&NCIPI

Abstract translation: 要解决的问题：与常规方法相比，提供更容易形成的膜，特别是氮化硅膜，氧化硅膜，氮氧化硅膜和碳化硅膜。 解决方案：在形成氮化硅，氧化硅，氮氧化硅或碳化硅膜期间添加至少一种非硅前体（例如锗前体和碳前体）改善沉积速率和/或允许性质 ，如压力，要调整的电影。 此外，在掺杂氧化硅或掺杂氮化硅或任何其它掺杂结构中，掺杂剂的存在可用于测量与掺杂剂相关联的信号（标记）作为蚀刻停止，或在其它情况下用于在 蚀刻。 版权所有（C）2006，JPO＆NCIPI

公开(公告)号：WO2008014228A3

公开(公告)日：2008-09-04

申请号：PCT/US2007074169

申请日：2007-07-24

Applicant: IBM ,  CHAKRAVARTI ASHIMA B ,  CHIDAMBARRAO DURESETI ,  HOLT JUDSON R ,  LIU YAOCHENG ,  RIM KERN

Inventor： CHAKRAVARTI ASHIMA B ,  CHIDAMBARRAO DURESETI ,  HOLT JUDSON R ,  LIU YAOCHENG ,  RIM KERN

IPC: H01L21/336

CPC classification number: H01L21/823864 ,  H01L21/76224 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/823878 ,  H01L29/165 ,  H01L29/66628 ,  H01L29/7843 ,  H01L29/7848

Abstract: An embedded silicon carbon (Si:C) having a substitutional carbon content in excess of one percent in order to effectively increase electron mobility by application of tension to a channel region of an NFET is achieved by overfilling a gap or trench formed by transistor gate structures with Si: C and polishing an etching the Si: C to or below a surface of a raised gate structure in a super-Damascene process, leaving Si:C only in selected regions above the transistor source and drain, even though processes capable of depositing Si: C with sufficiently high substitutional carbon content are inherently non-selective.

Abstract translation: 为了通过向NFET的沟道区施加张力而有效地增加电子迁移率，具有超过1％的替代碳含量的嵌入式硅碳（Si：C）通过过度填充由晶体管栅极结构形成的间隙或沟槽来实现 与Si：C并且在超级大马士革工艺中将Si：C蚀刻到凸起栅极结构的表面或其下方，即使能够沉积的工艺仅在晶体管源极和漏极之上的选定区域中留下Si：C 具有足够高取代碳含量的Si：C本质上是非选择性的。

公开(公告)号：SG140550A1

公开(公告)日：2008-03-28

申请号：SG2007059611

申请日：2007-08-15

Applicant: CHARTERED SEMICONDUCTOR MFG ,  IBM

Inventor： PING LIU JIN ,  MURPHY RICHARD J ,  MADAN ANITA ,  CHAKRAVARTI ASHIMA B

Abstract: Integrated circuit system With Carbon and Non-Carbon sILICON An integrated circuit system includes a substrate, a carbon-containing silicon region over the substrate, a non-carbon-containing silicon region over the substrate, and a silicon-carbon region, including the non-carbon- containing silicon region and the carbon-containing silicon region.

公开(公告)号：SG159522A1

公开(公告)日：2010-03-30

申请号：SG2010007722

申请日：2007-08-15

Applicant: CHARTERED SEMICONDUCTOR MFG ,  IBM

Inventor： PING LIU JIN ,  MURPHY RICHARD J ,  MADAN ANITA ,  CHAKRAVARTI ASHIMA B

Abstract: An integrated circuit system includes a substrate, a carbon-containing silicon region over the substrate, a non-carbon-containing silicon region over the substrate, and a silicon-carbon region, including the non-carbon- containing silicon region and the carbon-containing silicon region.