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    Bipolar capacitor driver
    2.
    发明授权
    Bipolar capacitor driver 失效
    双极电容驱动器

    公开(公告)号：US3656004A

    公开(公告)日：1972-04-11

    申请号：US3656004D

    申请日：1970-09-28

    Applicant: IBM

    Inventor： KEMERER DOUGLAS W ,  POMERANZ JEHOSHUA N

    IPC: H03K17/042 ,  H03K17/60 ,  H03K17/66 ,  H03K17/00

    CPC classification number: H03K17/04213 ,  H03K17/602 ,  H03K17/666

    Abstract: This specification discloses a bipolar driver which will charge a capacitive load to substantially the potential supplied to the driver. The driver includes two transistors that couple the load to a source of potential. One transistor is connected in shunt with the load while the other transistor is connected in series with the load and the source of potential. The shunt-connected transistor is used to discharge the capacitive load while the serially connected transistor is used to charge the capacitive load with charge from the source of potential. To allow the capacitive load to be charged to the full potential of the source, the driver includes circuitry which decouples the base of the serially connected transistor from the source of potential and drives the transistor with charge accumulated in the base-toemitter junction of the transistor so that the serially connected transistor will not be turned off until the potential across the capacitive load reaches the potential of the driving source.

    Abstract translation: 本说明书公开了一种双极驱动器，其将对容性负载充电至基本上提供给驱动器的电位。 驱动器包括将负载耦合到电位源的两个晶体管。 一个晶体管与负载分流连接，而另一个晶体管与负载和电位源串联连接。 分流连接的晶体管用于放电容性负载，而串联连接的晶体管用于从电势源的电荷对电容负载充电。 为了使容性负载被充电到电源的全部电位，驱动器包括使串联连接的晶体管的基极与电位源分离的电路，并驱动晶体管，其中电荷累积在基极 - 发射极结中 晶体管，使得串联的晶体管将不会被截止，直到电容负载两端的电位达到驱动源的电位。

    STATIC MEMORY CELL AND MEMORY ARRAY
    3.
    发明专利
    STATIC MEMORY CELL AND MEMORY ARRAY 审中-公开

    公开(公告)号：JP2002252287A

    公开(公告)日：2002-09-06

    申请号：JP2002004213

    申请日：2002-01-11

    Applicant: IBM

    Inventor： JASINSKI ERIC ,  KEMERER DOUGLAS W

    IPC: H01L27/11 ,  G11C5/06 ,  G11C11/412 ,  H01L21/8244

    Abstract: PROBLEM TO BE SOLVED: To provide a memory cell-array in which the minimum feature size of a design rule can be sufficiently used without considerably lowering production yield. SOLUTION: An electric power junction 160 extends zigzag into an adjoining line. Other electric power junctions 170 connect the electric power junctions of memory cells of adjoining columns with adjoining lines to each other. A subarray layout can be extended by reflection. A comparatively large amount of memory cell can be formed by lithographic exposure using step and repeat method. The layout of electric power junctions for memory cells considerably decrease the number of needed electric power junctions and/or the layout makes possible to form redundant junctions and shield meshes without increasing the number of needed junctions, further the enough use of the minimum future size become possible with increased production yield.

    TRANSISTOR CIRCUITS FOR CHARGING AND DISCHARGING A CAPACITIVE LOAD
    5.
    发明专利
    TRANSISTOR CIRCUITS FOR CHARGING AND DISCHARGING A CAPACITIVE LOAD 未知

    公开(公告)号：GB1299026A

    公开(公告)日：1972-12-06

    申请号：GB2982371

    申请日：1971-06-25

    Applicant: IBM

    Inventor： KEMERER DOUGLAS W ,  POMERANZ JEHOSHUA N

    IPC: H03K17/042 ,  H03K17/60 ,  H03K17/66

    Abstract: 1299026 Transistor switching circuits INTERNATIONAL BUSINESS MACHINES CORP 25 June 1971 [28 Sept 1970] 29823/71 Heading H3T In a circuit having a bipolar transistor T8 connected in series with a capacitive load CL to charge the capacitive load from a voltage source VH and a further bipolar transistor T5 connected in shunt with the load to discharge the load, a charge control means including a drive transistor T7 supplies drive from the source VH to the base of T8 for turning on T8 to charge the load and decouples the base of T8 from the source VH when the potential at the point A approaches the potential at the base of T7 so that the base-emitter capacitance of T8 supplies base drive to T8 to charge the point A to substantially the full potential of the voltage source VH. A voltage limiter consists of R 4 and diodes D1, D2, D3 and current flowing through R4 and D2 sets the anodes of D1 and D3 at 0À7 V above ground so that when the collector of any one of T1, T2 or T3 drops below ground diode D1 or D3 conducts and prevents the collector voltage dropping further. When the voltage at the inputs Vin, Vg are lower than at Vref the transistors T3, T4, T7 and T8 turn on and T1, T2, T5 and T6 turn off so that the capacitive load CL charges via T8. When the voltage across the load CL increases to reduce the base-emitter voltage (Vbe) across T7 to below one Vbe drop, T7 cuts off and T8 is maintained on due to the charge stored in the baseemitter capacitance CF of T8 until the potential at A approaches the supply potential VH. The time constant of the stray capacitance CS at the base of T7 and R5 should be smaller than the time constant CL and resistor R7. When the voltage at Vref to lower than that at Vin and Vg the transistors T1, T2 are on and T3 is off. This makes T4, T7, T8 off and T5, T6 on so that T5 discharges load capacitance CL. Diodes D4, D5 now turn on so that the charge on CL is used to drive T5 harder so as to speed up the discharge operation. Leakage resistor R10 prevents stray charge building up on capacitance CF and accidentally turning T8 on.

    MONOLITHIC MEMORY SENSE AMPLIFIER/BIT DRIVER HAVING ACTIVE BIT/SENSE LINE PULL-UP
    7.
    发明专利
    MONOLITHIC MEMORY SENSE AMPLIFIER/BIT DRIVER HAVING ACTIVE BIT/SENSE LINE PULL-UP 未知

    公开(公告)号：CA1012654A

    公开(公告)日：1977-06-21

    申请号：CA174371

    申请日：1973-06-19

    Applicant: IBM

    Inventor： DONOFRIO NICHOLAS M ,  KEMERER DOUGLAS W

    IPC: G11C11/41 ,  G11C11/414 ,  G11C11/416

    Abstract: The specification describes a sense amplifier/bit driver circuit having an active bit/sense line pull-up circuit. The active pull-up circuit is shown substantially as two transistors connected between the bit driver circuit and the bit/sense lines. A normal write operation is performed by pulling one bit/sense line to a down level (ground) potential and retaining the other bit/sense line at an up level (positive) voltage. Immediately after the write operation, recovery time is required to bring the down level bit/sense line back to the up level for subsequent read/write operations. The pull-up circuit described in the specification is turned on to perform this function and maintained off in order not to interfere with other operations.

    TIMED TRUE AND COMPLEMENT GENERATOR
    10.
    发明专利
    TIMED TRUE AND COMPLEMENT GENERATOR 未知

    公开(公告)号：CA985748A

    公开(公告)日：1976-03-16

    申请号：CA186190

    申请日：1973-11-19

    Applicant: IBM

    Inventor： DONOFRIO NICHOLAS M ,  KEMERER DOUGLAS W ,  RAYMOND JOHN JR

    IPC: H03M7/02 ,  H03K19/096

    Abstract: Disclosed is a true complement generator for providing the true and complement values of an input signal as an output, in response to predetermined timing signals. A first portion of the true complement generator is a gated inverter circuit generating a complement output. A second portion of the true complement generator is a gated driver circuit generating a true output. The true and complement phases of the input signal appear at the respective output nodes during the occurrence of a first timing signal, while both output nodes are held to the same level during the occurrence of a second timing signal.

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