公开(公告)号：WO02061826A3

公开(公告)日：2003-01-16

申请号：PCT/US0148819

申请日：2001-12-17

Applicant: INFINEON TECHNOLOGIES CORP

Inventor： LEHMANN GUNTHER ,  BRINTZENGER AXEL ,  DANIEL GABRIEL

IPC: H01L23/525

CPC classification number: H01L23/5252 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A semiconductor device is provided which is formed of a wafer (101) having on a surface thereof an area efficient arrangement of at least two antifuses (121, 122) in vertically stacked relation and sharing a common intermediate electrode (123) therebetween. The arrangement includes at least one lower antifuse (121) having a lower counter electrode (125) and a lower fusible insulator portion (124) defining a lower fuse element of an initial high electrical resistance state which interconnects the lower counter electrode (125) with the common intermediate electrode (123), and at least one upper antifuse (122), the upper antifuse (122) having an upper counter electrode (127) and an upper fusible insulator portion (126) defining an upper fuse element of an initial high electrical resistance state which interconnects the upper counter electrode (127) with the common intermediate electrode (123).

Abstract translation: 提供一种半导体器件，其由晶片（101）形成，晶片（101）在其表面上具有垂直堆叠关系的至少两个反熔丝（121,122）的区域有效布置，并且在其间共享公共中间电极（123）。 该装置包括至少一个具有下部对电极（125）和下部可熔绝缘体部分（124）的下部反熔丝（121），该下部可熔绝缘体部分（124）限定了初始高电阻状态的下部熔断元件，其将下部对置电极（125）与 公共中间电极（123）和至少一个上部反熔丝（122），上部反熔丝（122）具有上部对电极（127）和上部可熔绝缘体部分（126），其限定了初始高度的上部熔丝元件 将上部对置电极（127）与公共中间电极（123）相互连接的电阻状态。