公开(公告)号：JP2000222898A

公开(公告)日：2000-08-11

申请号：JP36513699

申请日：1999-12-22

Applicant: INFINEON TECHNOLOGIES CORP ,  IBM

Inventor： KIRIHATA TOSHIAKI ,  DANIEL GABRIEL

IPC: G11C11/401 ,  G11C29/00 ,  G11C29/04 ,  H01L21/82 ,  H01L21/8242 ,  H01L27/108

Abstract: PROBLEM TO BE SOLVED: To increase yield of chips while preventing signal contention of a sense amplifier using a high replacement flexibility redundancy and method. SOLUTION: Redundancy elements are integrated in at least two memory arrays which don't share the sense amplifiers. A defective row/column line in a first array or block is replaced with a redundant row/column line from its own redundancy. A corresponding row/column line whether defective or not is replaced in a second array or block which does not share sense amplifiers with the first block. The corresponding row/column line is replaced to mimic the redundancy replacement of the first block.

公开(公告)号：WO02061826A3

公开(公告)日：2003-01-16

申请号：PCT/US0148819

申请日：2001-12-17

Applicant: INFINEON TECHNOLOGIES CORP

Inventor： LEHMANN GUNTHER ,  BRINTZENGER AXEL ,  DANIEL GABRIEL

IPC: H01L23/525

CPC classification number: H01L23/5252 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A semiconductor device is provided which is formed of a wafer (101) having on a surface thereof an area efficient arrangement of at least two antifuses (121, 122) in vertically stacked relation and sharing a common intermediate electrode (123) therebetween. The arrangement includes at least one lower antifuse (121) having a lower counter electrode (125) and a lower fusible insulator portion (124) defining a lower fuse element of an initial high electrical resistance state which interconnects the lower counter electrode (125) with the common intermediate electrode (123), and at least one upper antifuse (122), the upper antifuse (122) having an upper counter electrode (127) and an upper fusible insulator portion (126) defining an upper fuse element of an initial high electrical resistance state which interconnects the upper counter electrode (127) with the common intermediate electrode (123).

Abstract translation: 提供一种半导体器件，其由晶片（101）形成，晶片（101）在其表面上具有垂直堆叠关系的至少两个反熔丝（121,122）的区域有效布置，并且在其间共享公共中间电极（123）。 该装置包括至少一个具有下部对电极（125）和下部可熔绝缘体部分（124）的下部反熔丝（121），该下部可熔绝缘体部分（124）限定了初始高电阻状态的下部熔断元件，其将下部对置电极（125）与 公共中间电极（123）和至少一个上部反熔丝（122），上部反熔丝（122）具有上部对电极（127）和上部可熔绝缘体部分（126），其限定了初始高度的上部熔丝元件 将上部对置电极（127）与公共中间电极（123）相互连接的电阻状态。

公开(公告)号：WO0233707A2

公开(公告)日：2002-04-25

申请号：PCT/US0145044

申请日：2001-10-19

Applicant: INFINEON TECHNOLOGIES CORP

Inventor： LEHMANN GUNTHER ,  DANIEL GABRIEL ,  FRANKOWSKY GERD

IPC: G11C17/16 ,  G11C17/18 ,  G11C17/00

CPC classification number: G11C17/18 ,  G11C17/16

Abstract: A circuit for programming electrical fuses, in accordance with the present invention, includes a shift register (12) including a plurality of latches (16). Each latch has a corresponding switch (22) and a corresponding electrical fuse (24). A bit generator (208) generates a single bit of a first state and all other bits of a second state. The bit generator propagates the generated bits into the shift register in accordance with a clock signal (206). Each switch enables conduction through the corresponding electrical fuse in accordance with the generated bits stored in the corresponding latch. A blow voltage line (28) connects to the electrical fuses. The blow voltage line is activated to blow fuses in accordance with programming data (202) such that the electrical fuses are programmed in accordance with the programming data when the single bit of the first state is stored in the latch corresponding to the fuse to be programmed.

Abstract translation: 根据本发明的用于编程电熔丝的电路包括包括多个闩锁（16）的移位寄存器（12）。 每个闩锁具有对应的开关（22）和相应的电熔丝（24）。 位产生器（208）产生第一状态的单个位和第二状态的所有其他位。 位产生器根据时钟信号将生成的比特传播到移位寄存器（206）。 每个开关根据存储在相应的锁存器中的产生的位使能通过相应的电熔丝的导通。 吹电压线（28）连接到电保险丝。 根据编程数据（202）激活吹扫电压线以熔断熔丝，使得当第一状态的单个位被存储在对应于要编程的熔丝的锁存器中时，电熔丝根据编程数据被编程 。

公开(公告)号：DE60110297D1

公开(公告)日：2005-06-02

申请号：DE60110297

申请日：2001-02-23

Applicant: INFINEON TECHNOLOGIES CORP ,  IBM

Inventor： KIRIHATA TOSHIAKI ,  DANIEL GABRIEL

IPC: G11C11/413 ,  G11C11/401 ,  G11C29/00 ,  G11C29/04 ,  G06F11/20

Abstract: A memory device that includes a plurality of data storage cells; at least one redundancy data storage cell; a redundancy match detection circuit; and a means for coupling programmable fuses to the redundancy match detection circuit, wherein a defective data storage is replaced by one redundancy data storage when the redundancy match detection detects a pre-determined condition set by said programmable fuse is described. Decoding is accomplished by a data bus selecting the e-fuse to be blown. The data bus is also used for reading the state of the e-fuses to ensure that the e-fuses are correctly blown. Power is effectively applied to the selected e-fuses while sharing the data bus for e-fuse decoding and verification. In order to reduce the number of communication channels between e-fuses and the redundancy match detection circuitry, the transfer operation uses time multiplexing, allowing e-fuse information to be transferred to the redundancy match detection circuitry sequentially. The actual time multiplexing operation for performing the transfer is preferably enabled only after the chip power-up state.

公开(公告)号：HK1034804A1

公开(公告)日：2001-11-02

申请号：HK01105209

申请日：2001-07-26

Applicant: INFINEON TECHNOLOGIES CORP

Inventor： NARAYAN CHANDRASEKHAR ,  ARNDT KENNETH ,  LACHTRUPP DAVID ,  BRINTZINGER AXEL ,  DANIEL GABRIEL ,  KIRIHATA TOSHIAKI

IPC: H01L21/82 ,  H01H85/00 ,  H01H85/02 ,  H01H85/044 ,  H01H85/046 ,  H01L21/66 ,  H01L23/525 ,  H01L27/02 ,  H01L

Abstract: A plurality of fuses of different types, each type of fuse serving a specific purpose are positioned on a semiconductor integrated circuit wafer, wherein activating one type of fuse does not incapacitate fuses of a different type. Fuses of the first type, e.g., laser activated fuses, are primarily used for repairing defects at the wafer level, whereas fuses of the second type, e.g., electrically activated fuses, are used for repairing defects found after mounting the IC chips on a module and stressing the module at burn-in test. Defects at the module level typically are single cell failures which are cured by the electrically programmed fuses to activate module level redundancies.

公开(公告)号：DE69911364D1

公开(公告)日：2003-10-23

申请号：DE69911364

申请日：1999-12-20

Applicant: INFINEON TECHNOLOGIES CORP ,  IBM

Inventor： KIRIHATA TOSHIAKI ,  DANIEL GABRIEL

IPC: G11C11/401 ,  G11C29/00 ,  G11C29/04 ,  H01L21/82 ,  H01L21/8242 ,  H01L27/108 ,  G06F11/20

Abstract: The present disclosure relates to semiconductor memories and more particularly, to an improved method and apparatus for replacing defective row/column lines. In accordance with the present invention, a high replacement flexibility redundancy and method is employed to increase chip yield and prevent sense amplifier signal contention. Redundancy elements are integrated in at least two of a plurality of memory arrays, which don't share the sense amplifiers. Thus, no additional sense amplifiers are required. A defective row/column line in a first array or block is replaced with a redundant row/column line from its own redundancy. A corresponding row/column line whether defective or not is replaced in a second array or block, which does not share sense amplifiers with the first block. The corresponding row/column is replaced to mimic the redundancy replacement of the first block thereby increasing flexibility and yield as well as preventing sensing signal contention.

公开(公告)号：DE69911364T2

公开(公告)日：2004-07-22

申请号：DE69911364

申请日：1999-12-20

Applicant: INFINEON TECHNOLOGIES CORP ,  IBM

Inventor： KIRIHATA TOSHIAKI ,  DANIEL GABRIEL

IPC: G11C11/401 ,  G11C29/00 ,  G11C29/04 ,  H01L21/82 ,  H01L21/8242 ,  H01L27/108 ,  G06F11/20

Abstract: The present disclosure relates to semiconductor memories and more particularly, to an improved method and apparatus for replacing defective row/column lines. In accordance with the present invention, a high replacement flexibility redundancy and method is employed to increase chip yield and prevent sense amplifier signal contention. Redundancy elements are integrated in at least two of a plurality of memory arrays, which don't share the sense amplifiers. Thus, no additional sense amplifiers are required. A defective row/column line in a first array or block is replaced with a redundant row/column line from its own redundancy. A corresponding row/column line whether defective or not is replaced in a second array or block, which does not share sense amplifiers with the first block. The corresponding row/column is replaced to mimic the redundancy replacement of the first block thereby increasing flexibility and yield as well as preventing sensing signal contention.

公开(公告)号：EP1128269A8

公开(公告)日：2001-11-28

申请号：EP01301643

申请日：2001-02-23

Applicant: INFINEON TECHNOLOGIES CORP ,  IBM

Inventor： KIRIHATA TOSHIAKI ,  DANIEL GABRIEL

IPC: G11C11/413 ,  G11C11/401 ,  G11C29/00 ,  G11C29/04 ,  G06F11/20

CPC classification number: G11C29/802

Abstract: A memory device that includes a plurality of data storage cells; at least one redundancy data storage cell; a redundancy match detection circuit; and a means for coupling programmable fuses to the redundancy match detection circuit, wherein a defective data storage is replaced by one redundancy data storage when the redundancy match detection detects a pre-determined condition set by said programmable fuse is described. Decoding is accomplished by a data bus selecting the e-fuse to be blown. The data bus is also used for reading the state of the e-fuses to ensure that the e-fuses are correctly blown. Power is effectively applied to the selected e-fuses while sharing the data bus for e-fuse decoding and verification. In order to reduce the number of communication channels between e-fuses and the redundancy match detection circuitry, the transfer operation uses time multiplexing, allowing e-fuse information to be transferred to the redundancy match detection circuitry sequentially. The actual time multiplexing operation for performing the transfer is preferably enabled only after the chip power-up state.