公开(公告)号：JP2000231535A

公开(公告)日：2000-08-22

申请号：JP32395199

申请日：1999-11-15

Applicant: INFINEON TECHNOLOGIES CORP

Inventor： FLECK ROD G ,  OBERLAENDER KLAUS ,  BAROR GIGY ,  EDER ALFRED ,  NGUYEN LE TRONG

IPC: G06F9/30 ,  G06F12/00 ,  G06F12/06 ,  G06F13/16

Abstract: PROBLEM TO BE SOLVED: To provide a data processing unit which has a coupling unit for data transfer. SOLUTION: This data processing unit is provided with a register file 8 having plural registers, a memory having plural n-bit input/output ports, a coupling unit for connecting the memory to the register file and a memory address and a selection unit 9 for addressing a memory bank. The coupling unit includes at least a bus which forms 1st and 2nd sub buses and has at least 2n-bit bus width, a 1st coupler for selectively connecting each memory bank or register file to one of the sub buses and a 2nd coupler for connecting the register file or a memory bank to the buses.

公开(公告)号：DE69908772D1

公开(公告)日：2003-07-17

申请号：DE69908772

申请日：1999-02-25

Applicant: INFINEON TECHNOLOGIES CORP

Inventor： ARNOLD D ,  EDER ALFRED

IPC: G06F9/42 ,  G06F9/30 ,  G06F9/46 ,  G06F9/48 ,  G11C7/00

Abstract: The present invention relates to a data processing unit, comprising at least one register having at least one read port and one write port. The register has at least two memory cells each having a write line and a read line, a first switch having inputs and one output for coupling said read line of one of said memory cells with said read port, second switch for coupling said write line of one of said memory cells with said write port.

公开(公告)号：DE69908772T2

公开(公告)日：2004-07-08

申请号：DE69908772

申请日：1999-02-25

Applicant: INFINEON TECHNOLOGIES CORP

Inventor： ARNOLD D ,  EDER ALFRED

IPC: G06F9/42 ,  G06F9/30 ,  G06F9/46 ,  G06F9/48 ,  G11C7/00

Abstract: The present invention relates to a data processing unit, comprising at least one register having at least one read port and one write port. The register has at least two memory cells each having a write line and a read line, a first switch having inputs and one output for coupling said read line of one of said memory cells with said read port, second switch for coupling said write line of one of said memory cells with said write port.