公开(公告)号：JP2001189080A

公开(公告)日：2001-07-10

申请号：JP37570099

申请日：1999-12-28

Applicant: INFINEON TECHNOLOGIES CORP

Inventor： MUELLER GERHARD ,  HOENIGSCHMID HEINZ

IPC: G11C11/409 ,  G11C16/06

Abstract: PROBLEM TO BE SOLVED: To reduce size of a sense amplifier without degrading capability or functionality of a sense amplifier. SOLUTION: This device has a latch coupled to a first bit line and a second bit line, and a driver having an input side and an output side connected to the latch, this driver is operated so that an active input signal activating this driver is received, over-drive voltage is increased by this active input signal, and the driver is operated with an amplified over-drive mode.

公开(公告)号：WO02059973A3

公开(公告)日：2003-04-10

申请号：PCT/US0201919

申请日：2002-01-24

Applicant: INFINEON TECHNOLOGIES CORP

Inventor： HOENIGSCHMID HEINZ

IPC: G11C11/15 ,  G11C11/16 ,  H01L21/8246 ,  H01L27/105 ,  H01L27/22 ,  H01L27/115 ,  G11C11/02

CPC classification number: H01L27/228 ,  B82Y10/00 ,  G11C11/16

Abstract: An MRAM device (100) and method of manufacturing thereof having magnetic memory storage cells or stacks (MS0, MS1, MS2, MS3) coupled together in series. Devices (X0, X1, X2, and X3) are coupled in parallel to each magnetic memory storage cell (MS0, MS1, MS2, MS3). The active are (AA) is continuous, and contact vias (VU1, VL1, VU2, VL2 and VU3) are shared by magnetic stacks (MS0, MS1, MS2, MS3). N+ regions (108, 110, 112, 114, 116, 118) are coupled together by devices (X0, X1, X2, and X3).

Abstract translation: 一种MRAM器件（100）及其制造方法，其具有串联耦合在一起的磁存储器存储单元或堆栈（MS0，MS1，MS2，MS3）。 器件（X0，X1，X2和X3）并联耦合到每个磁存储器存储单元（MS0，MS1，MS2，MS3）。 有源（AA）是连续的，并且接触通孔（VU1，VL1，VU2，VL2和VU3）由磁性堆栈（MS0，MS1，MS2，MS3）共享。 N +区域（108,110,112,114,116,118）由器件（X0，X1，X2和X3）耦合在一起。

公开(公告)号：DE60030820D1

公开(公告)日：2006-11-02

申请号：DE60030820

申请日：2000-10-19

Applicant: INFINEON TECHNOLOGIES CORP ,  IBM

Inventor： HAFFNER HENNING ,  HOENIGSCHMID HEINZ ,  SAMUELS DONALD J

IPC: G03F7/20 ,  G03F1/00

Abstract: A method, and a system for employing the method, for providing a modified optical proximity correction (OPC) for correcting distortions of pattern lines on a semiconductor circuit wafer. The method comprises producing a mask having one or more pattern regions, and producing the semiconductor circuit wafer from the mask. The pattern regions include one or more non-edge pattern regions located adjacent to other of the non-edge pattern regions on the mask. The pattern regions further include one or more edge pattern regions located at or near an area on the mask not having the other non-edge pattern regions. The edge pattern regions have widths calculated to minimize the variance in dimensions between one or more pattern lines on the semiconductor circuit wafer formed from them and one or more pattern lines on the semiconductor circuit wafer formed from the non-edge pattern regions. The distances between any two of the pattern regions are calculated to minimize the variance in dimensions between the one or more pattern lines formed from the edge pattern regions and the one or more pattern lines formed from the non-edge pattern regions. The above producing step includes producing the semiconductor circuit wafer from the mask having the pattern lines formed from the non-edge pattern regions and having the pattern lines formed from the edge pattern regions, where the pattern lines formed from the non-edge regions are permitted to differ in distances between them.