公开(公告)号：DE60030820D1

公开(公告)日：2006-11-02

申请号：DE60030820

申请日：2000-10-19

Applicant: INFINEON TECHNOLOGIES CORP ,  IBM

Inventor： HAFFNER HENNING ,  HOENIGSCHMID HEINZ ,  SAMUELS DONALD J

IPC: G03F7/20 ,  G03F1/00

Abstract: A method, and a system for employing the method, for providing a modified optical proximity correction (OPC) for correcting distortions of pattern lines on a semiconductor circuit wafer. The method comprises producing a mask having one or more pattern regions, and producing the semiconductor circuit wafer from the mask. The pattern regions include one or more non-edge pattern regions located adjacent to other of the non-edge pattern regions on the mask. The pattern regions further include one or more edge pattern regions located at or near an area on the mask not having the other non-edge pattern regions. The edge pattern regions have widths calculated to minimize the variance in dimensions between one or more pattern lines on the semiconductor circuit wafer formed from them and one or more pattern lines on the semiconductor circuit wafer formed from the non-edge pattern regions. The distances between any two of the pattern regions are calculated to minimize the variance in dimensions between the one or more pattern lines formed from the edge pattern regions and the one or more pattern lines formed from the non-edge pattern regions. The above producing step includes producing the semiconductor circuit wafer from the mask having the pattern lines formed from the non-edge pattern regions and having the pattern lines formed from the edge pattern regions, where the pattern lines formed from the non-edge regions are permitted to differ in distances between them.

公开(公告)号：JP2001189080A

公开(公告)日：2001-07-10

申请号：JP37570099

申请日：1999-12-28

Applicant: INFINEON TECHNOLOGIES CORP

Inventor： MUELLER GERHARD ,  HOENIGSCHMID HEINZ

IPC: G11C11/409 ,  G11C16/06

Abstract: PROBLEM TO BE SOLVED: To reduce size of a sense amplifier without degrading capability or functionality of a sense amplifier. SOLUTION: This device has a latch coupled to a first bit line and a second bit line, and a driver having an input side and an output side connected to the latch, this driver is operated so that an active input signal activating this driver is received, over-drive voltage is increased by this active input signal, and the driver is operated with an amplified over-drive mode.

公开(公告)号：WO02059973A3

公开(公告)日：2003-04-10

申请号：PCT/US0201919

申请日：2002-01-24

Applicant: INFINEON TECHNOLOGIES CORP

Inventor： HOENIGSCHMID HEINZ

IPC: G11C11/15 ,  G11C11/16 ,  H01L21/8246 ,  H01L27/105 ,  H01L27/22 ,  H01L27/115 ,  G11C11/02

CPC classification number: H01L27/228 ,  B82Y10/00 ,  G11C11/16

Abstract: An MRAM device (100) and method of manufacturing thereof having magnetic memory storage cells or stacks (MS0, MS1, MS2, MS3) coupled together in series. Devices (X0, X1, X2, and X3) are coupled in parallel to each magnetic memory storage cell (MS0, MS1, MS2, MS3). The active are (AA) is continuous, and contact vias (VU1, VL1, VU2, VL2 and VU3) are shared by magnetic stacks (MS0, MS1, MS2, MS3). N+ regions (108, 110, 112, 114, 116, 118) are coupled together by devices (X0, X1, X2, and X3).

Abstract translation: 一种MRAM器件（100）及其制造方法，其具有串联耦合在一起的磁存储器存储单元或堆栈（MS0，MS1，MS2，MS3）。 器件（X0，X1，X2和X3）并联耦合到每个磁存储器存储单元（MS0，MS1，MS2，MS3）。 有源（AA）是连续的，并且接触通孔（VU1，VL1，VU2，VL2和VU3）由磁性堆栈（MS0，MS1，MS2，MS3）共享。 N +区域（108,110,112,114,116,118）由器件（X0，X1，X2和X3）耦合在一起。

公开(公告)号：JP2000077630A

公开(公告)日：2000-03-14

申请号：JP21500599

申请日：1999-07-29

Applicant: Internatl Business Mach Corp ,  Siemens Ag ,  インターナショナル・ビジネス・マシーンズ・コーポレイション ,  シーメンス・アクチェンゲゼルシャフト

Inventor： HOENIGSCHMID HEINZ ,  NETIS DMITRY

IPC: H01L27/06 ,  G11C11/407 ,  H01L21/8234 ,  H01L21/8242 ,  H01L27/088 ,  H01L27/10 ,  H01L27/105 ,  H01L27/108

CPC classification number: H01L27/108 ,  H01L27/105

Abstract: PROBLEM TO BE SOLVED: To reduce the area occupied by a circuit on an IC by allowing each conductor pattern to comprise one or plural ring parts surrounding an element diffusion contact-point region, while a ring part forms the gate conductor of an insulated gate field effect transistor(IGFET).
SOLUTION: A word line driver circuit 40, for example, comprises a plurality of ring field-effect transistor(IGFET) elements 42, with each of them provided with a ring conductor 44, while a drain region 46 is provided in the ring conductor 44, with a source region 48 provided outside the ring conductor 44. A single- line connection conductor 50 is provided between the ring IGFET elements 42, to allow conductive connection of the ring IGFET elements 42. With this configuration, the length of each transistor is increased, thus increasing the channel width of the transistor 42. The ring part is formed of a conductor pattern comprising the width of almost one minimum feature size F, with the interval between adjoining conductor patterns kept about 4F or less.
COPYRIGHT: (C)2000,JPO

Abstract translation: 要解决的问题：为了通过允许每个导体图案包括围绕元件扩散接触点区域的一个或多个环形部分来减小IC上的电路占据的面积，而环形成绝缘栅极场的栅极导体 效应晶体管（IGFET）。 解决方案：例如，字线驱动器电路40包括多个环形场效应晶体管（IGFET）元件42，其中每个元件设置有环形导体44，而漏极区域46设置在环形导体44中 ，源区域48设置在环形导体44的外部。在环形IGFET元件42之间提供单线连接导体50，以允许环形IGFET元件42的导电连接。利用该配置，每个晶体管的长度为 增加，从而增加了晶体管42的沟道宽度。环部分由包括几乎一个最小特征尺寸F的宽度的导体图案形成，相邻导体图案之间的间隔保持在约4°F或更小。

公开(公告)号：JP2000022100A

公开(公告)日：2000-01-21

申请号：JP13219499

申请日：1999-05-13

Applicant: IBM ,  SIEMENS AG

Inventor： HOENIGSCHMID HEINZ ,  HSU LOUIS LU-CHEN ,  MANDELMAN JACK ALLAN

IPC: H01L27/10 ,  H01L21/8242 ,  H01L27/108

Abstract: PROBLEM TO BE SOLVED: To provide a structure related to a semiconductor memory cell whose size is less than 4.5F2 in a case where F denotes the minimum dimension of a lithography techinique, and a manufacturing method thereof. SOLUTION: A semiconductor memory cell comprises a memory capacitor 12 formed in a trench, a transfer device formed in a mesa region which extends on the substantial arc of the periphery of the trench and is electrically isolated, and a buried strap which electrically connects the transfer device to the memory capacitors, wherein the transfer device comprises a controlled conduction channel located at a prescribed position on the arc removed from the buried strap.

公开(公告)号：JPH11163299A

公开(公告)日：1999-06-18

申请号：JP27395598

申请日：1998-09-28

Applicant: SIEMENS AG ,  IBM

Inventor： MUELLER GERHARD ,  KIRIHATA TOSHIAKI ,  HOENIGSCHMID HEINZ

IPC: H01L27/108 ,  G11C7/18 ,  G11C11/4097 ,  H01L21/8242

Abstract: PROBLEM TO BE SOLVED: To provide an improved architecture, in which an area penalty is reduced or there is substantially no area penalty in a high-density memory, using a diagonal bit line. SOLUTION: This semiconductor memory has a plurality of diagonal bit lines, having changes in the horizontal direction along a memory cell array 12 for facilitating the access to memory cells and being arranged in a pattern shape and a plurality of dual word lines which are not crossed at right angles with the bit lines, the dual word lines contain a master word line 22 in a first layer and a plurality of local word lines in a second layer, and the local word lines are solved by connection to the master word line 22 in a common line via electrical connections disposed at a plurality of intervals.

公开(公告)号：WO2004112048A3

公开(公告)日：2005-04-07

申请号：PCT/EP2004006019

申请日：2004-06-03

Applicant: INFINEON TECHNOLOGIES AG ,  IBM ,  DEBROSSE JOHN ,  HOENIGSCHMID HEINZ ,  LEUSCHNER RAINER ,  MUELLER GERHARD

Inventor： DEBROSSE JOHN ,  HOENIGSCHMID HEINZ ,  LEUSCHNER RAINER ,  MUELLER GERHARD

IPC: G06F11/10 ,  G11C7/24 ,  G11C11/406 ,  G11C29/00 ,  G11C11/15

CPC classification number: G11C7/24 ,  G06F11/106 ,  G11C11/406

Abstract: The present invention relates to a method and apparatus for reducing data errors in a magneto-resistive random access memory (MRAM). According to the disclosed method, data bits and associated error correction code (ECC) check bits are stored into a storage area. Thereafter, the data bits and ECC check bits are read out and any errors are detected and corrected. A data refresh is then initiated based on a count and data bits and associated ECC check bits stored in the storage area are then refreshed by accessing the stored data bits and the associated ECC check bits, and ultimately by checking, correcting and restoring the data bits and the ECC check bits to the storage area.

Abstract translation: 本发明涉及一种用于减少磁阻随机存取存储器（MRAM）中的数据错误的方法和装置。 根据所公开的方法，将数据位和相关联的纠错码（ECC）校验位存储到存储区域中。 此后，读出数据位和ECC校验位，并检测和校正任何错误。 然后基于计数开始数据刷新，然后通过访问存储的数据位和相关联的ECC校验位来刷新存储在存储区域中的相关ECC校验位，并且最终通过检查，校正和恢复数据位 并将ECC校验位存储到存储区域。

公开(公告)号：JPH11265574A

公开(公告)日：1999-09-28

申请号：JP37452498

申请日：1998-12-28

Applicant: SIEMENS AG ,  IBM

Inventor： HOENIGSCHMID HEINZ ,  KLEINHENZ RICHARD L ,  MANDELMAN JACK A

IPC: G11C11/408 ,  G11C5/14 ,  G11C11/403 ,  G11C11/4074

Abstract: PROBLEM TO BE SOLVED: To make a standby operation mode in which a leakage current is reduced executable by obtaining whether a DRAM is in the standby operation mode or in a normal operation mode and turning a first power source with respect to the array of the DRAM off when the DRAM is in the standby operation mode and maintaing the first power source with respect to the array of the DRAM when it is in the normal operation mode. SOLUTION: A collar 268 is provided at the upward part of a trench in order to separate a p-well from a storage node, an n-well area or an n-band area exists at the downward direction of the p-weel and the embedding plate 265 of capacitances in these n areas is connected to the embedding plates of other DRAM cells of the array. The reducing of stand-by currents is achieved by switching off a voltage generator or a voltage pump supplying a proper voltage to the n-well during the stanby mode and the voltage pump for the n-band with respect to the array of the DRAM is kept as switched on.

公开(公告)号：JPH1187641A

公开(公告)日：1999-03-30

申请号：JP18405498

申请日：1998-06-30

Applicant: SIEMENS AG ,  IBM

Inventor： HOENIGSCHMID HEINZ ,  DEBROSSE JOHN

IPC: H01L21/8242 ,  H01L27/108

Abstract: PROBLEM TO BE SOLVED: To minimize or eliminate the area required for twisting a bit line in order to reduce the size of a dynamic random access memory, wherein each cell of a memory cell array is addressed by a word line and a bit line. SOLUTION: A lower part metal layer and an upper part metal layer, together with a dielectric layer allocated between them are provided. A first bit line among a plurality of bit lines comprises a lower part metal first bit line part mounted on the lower part metal layer, and the lower part metal first bit line part is combined to first multiple memory cells. Further, the first bit line comprises an upper part metal first bit line part mounted on the upper part metal layer also, and the upper part metal first bit line part is combined to the lower part metal first bit line part by a first contact which penetrates a dielectric layer. The first contact is allocated with one of active areas 522, 530, and 560.

公开(公告)号：DE602004021187D1

公开(公告)日：2009-07-02

申请号：DE602004021187

申请日：2004-06-03

Applicant: INFINEON TECHNOLOGIES AG ,  IBM

Inventor： DEBROSSE JOHN ,  HOENIGSCHMID HEINZ ,  LEUSCHNER RAINER ,  MUELLER GERHARD

IPC: G11C29/00 ,  G06F11/10 ,  G11C7/24 ,  G11C11/15 ,  G11C11/406

Abstract: The present invention relates to a method and apparatus for reducing data errors in a magneto-resistive random access memory (MRAM). According to the disclosed method, data bits and associated error correction code (ECC) check bits are stored into a storage area. Thereafter, the data bits and ECC check bits are read out and any errors are detected and corrected. A data refresh is then initiated based on a count and data bits and associated ECC check bits stored in the storage area are then refreshed by accessing the stored data bits and the associated ECC check bits, and ultimately by checking, correcting and restoring the data bits and the ECC check bits to the storage area.