公开(公告)号：JP2000251468A

公开(公告)日：2000-09-14

申请号：JP2000034052

申请日：2000-02-10

Applicant: INFINEON TECHNOLOGIES CORP ,  IBM

Inventor： JI BRIAN ,  MUELLER GERHARD ,  KIRIHATA TOSHIAKI ,  HANSON DAVID

IPC: G11C11/407 ,  G11C7/10 ,  G11C11/409

Abstract: PROBLEM TO BE SOLVED: To increase data speed or band width by arranging a pre-fetch circuit so that data speed among each hierarchy stage is all equalized substantially and controlling a latch so that the respective data speed at each hierarchy stage is all maintained. SOLUTION: Stages A-C have different data speed/signal time (data speed/bit) a, b, c respectively. Data speed at each stage is determined by data speed/signal path (selected by the number of signal path that is the number of pre-fetch). Pre-fetch is constituted between stages A-B of m>=int(a/b), pre-fetch is constituted between stages B-C of n>=int(b/c), and integers m, n are adjusted as desired. In order to vary pre-fetch depth at each stage, a pointer is designed so as to correspond to pre-fetch depth. A pointer signal is supplied by using a control circuit 214, the control circuit 214 latches continuously data made to synchronize with the latch included in a pre-fetch circuit, and timing is performed optimally.

公开(公告)号：JP2001189080A

公开(公告)日：2001-07-10

申请号：JP37570099

申请日：1999-12-28

Applicant: INFINEON TECHNOLOGIES CORP

Inventor： MUELLER GERHARD ,  HOENIGSCHMID HEINZ

IPC: G11C11/409 ,  G11C16/06

Abstract: PROBLEM TO BE SOLVED: To reduce size of a sense amplifier without degrading capability or functionality of a sense amplifier. SOLUTION: This device has a latch coupled to a first bit line and a second bit line, and a driver having an input side and an output side connected to the latch, this driver is operated so that an active input signal activating this driver is received, over-drive voltage is increased by this active input signal, and the driver is operated with an amplified over-drive mode.

公开(公告)号：JP2000244471A

公开(公告)日：2000-09-08

申请号：JP2000035979

申请日：2000-02-14

Applicant: INFINEON TECHNOLOGIES CORP ,  IBM

Inventor： HANSON DAVID R ,  MUELLER GERHARD

IPC: H03K5/00 ,  G11C7/10 ,  G11C7/22 ,  G11C11/4096 ,  H04J3/06 ,  H04L7/00 ,  H04L7/02 ,  H04L25/40

Abstract: PROBLEM TO BE SOLVED: To provide a synchronous data fetch circuit that synchronously captures data at a frequency substantially higher than a frequency of each data line and can use a step-down voltage signal. SOLUTION: The synchronous data fetch circuit 200 is provided with a timer generator 206 provided with a 1st timer generator output side, a 1st data driver circuit 210 consisting of a plurality of data drivers that receives a plurality of 1st data signals and a plurality of timing signals, and a 1st data clock circuit 214 that receives a data stream with a 1st high frequency and a 1st high frequency timing pulse stream. Thus, fetch of data in the 1st high frequency data stream is synchronized by using the 1st high frequency timing pulse stream and a synchronized data capture signal is outputted.

公开(公告)号：JP2000244470A

公开(公告)日：2000-09-08

申请号：JP2000035978

申请日：2000-02-14

Applicant: INFINEON TECHNOLOGIES CORP ,  IBM

Inventor： HANSON DAVID RUSSELL ,  MUELLER GERHARD

IPC: G11C11/413 ,  G11C7/10 ,  G11C11/407 ,  G11C11/409 ,  G11C11/417 ,  H03K5/00 ,  H04L7/00 ,  H04L7/02 ,  H04L25/40

Abstract: PROBLEM TO BE SOLVED: To reduce power consumption and/or to improve performance by receiving the data signal and the timing signal of full swing as inputs, converting them into voltage levels that are stepped down and synchronizing the data/ timing signals with voltage level signals that are stepped down. SOLUTION: This data synchronization take-in circuit 200 can receive/output a full swing signal and synchronizes data take-in by generating and using a step-down signal. A timing driver circuit 202 receives a full swing timing signal by an input node 208. The timing driver circuit 202 not only adds delay required for taking in appropriate data in a reception circuit to the full swing timing signal but also shifts the voltage level of the timing signal and outputs the timing signal which is stepped down. The voltage level of the timing signal which is stepped down is stepped down and the stepped down level is lower than the voltage level of the full swing signal.

公开(公告)号：JP2000286693A

公开(公告)日：2000-10-13

申请号：JP2000063779

申请日：2000-03-08

Applicant: INFINEON TECHNOLOGIES CORP ,  IBM

Inventor： HANSON DAVID R ,  MUELLER GERHARD

IPC: G11C11/409 ,  G11C7/10 ,  G11C11/4096 ,  G11C11/41 ,  G11C11/417 ,  H03K19/017 ,  H03K19/0175

Abstract: PROBLEM TO BE SOLVED: To provide an improved driver circuit which can increase a charge rate to attain an operation faster than an IC by increasing the current of the driver output and operating the driver circuit in an increased overdrive mode. SOLUTION: An overdrive sub-circuit 240 includes an overdrive output 248 which is connected to a driver input 273. The offset set to an active control output signal is supplied to the circuit 240 and the circuit 240 generates an active overdrive output signal to increase the level of overdrive voltage. The overdrive voltage represents the difference between the gate-source voltage and the threshold voltage of a driver transistor. The increased overdrive voltage results in the operation of the driver transistor in an increased overdrive mode, thus improving the performance of the driver transistor.

公开(公告)号：JP2000235793A

公开(公告)日：2000-08-29

申请号：JP2000000202

申请日：2000-01-05

Applicant: INFINEON TECHNOLOGIES CORP ,  IBM

Inventor： HANSON DAVID R ,  MUELLER GERHARD

IPC: G11C11/41 ,  G11C7/10 ,  G11C11/409 ,  G11C11/4096 ,  G11C11/417 ,  H03K19/017

Abstract: PROBLEM TO BE SOLVED: To provide a driver circuit in which a charge rate is increased to operate a semiconductor device with a high clock cycle. SOLUTION: A memory chip has plural first sense amplifier 14. The plural first sense amplifiers 14 are multiplexed by MUX16 and connected to a second sense amplifier 24 through global data bus MDQ and bMDQ. The first sense amplifiers detect electric charges from a memory array cell of a memory array, the second sense amplifier 24 translates this charges to a higher level (DOUT), and this high level is expelled by an off-chip driver from a chip. A changing circuit 22 is connected to the global data bus MDQ and bMDQ, and comprises a driver circuit which can charge the global data bus with an increased rate.

公开(公告)号：WO0193273A3

公开(公告)日：2002-08-08

申请号：PCT/US0117441

申请日：2001-05-31

Applicant: INFINEON TECHNOLOGIES CORP ,  IBM

Inventor： MUELLER GERHARD ,  KIRIHATA TOSHIAKI ,  NETIS DMITRY

IPC: G11C7/12 ,  G11C7/18 ,  G11C8/12 ,  G11C11/4094 ,  G11C11/4097 ,  G11C7/10

CPC classification number: G11C11/4094 ,  G11C7/12 ,  G11C7/18 ,  G11C8/12 ,  G11C11/4097

Abstract: There is provided a semiconductor memory device that includes: a plurality of memory cells arranged in at least two groups (102); at least one sense amplifier (SA); a first and a second multiplexer (MUXs); and at least one programmable control device (control circuit). Each multiplexer is adapted to couple at least one of the groups to the amplifier. The programmable control device is adapted to control the first and said second multiplexers. In one embodiment, the programmable control device is adapted to control the multiplexers independently.

Abstract translation: 提供了一种半导体存储器件，其包括：布置在至少两组（102）中的多个存储单元; 至少一个读出放大器（SA）; 第一和第二多路复用器（MUX）; 和至少一个可编程控制装置（控制电路）。 每个多路复用器适于将至少一个组耦合到放大器。 可编程控制装置适于控制第一和第二多路复用器。 在一个实施例中，可编程控制装置适于独立地控制多路复用器。

公开(公告)号：WO0143135A9

公开(公告)日：2002-05-16

申请号：PCT/US0032921

申请日：2000-12-05

Applicant: INFINEON TECHNOLOGIES CORP ,  IBM

Inventor： HANSON DAVID R ,  KIRIHATA TOSHIAKI ,  MUELLER GERHARD

IPC: G11C11/409 ,  G11C7/10 ,  G11C11/407 ,  H03K17/22 ,  H03K19/0175

CPC classification number: G11C7/1072 ,  G11C7/1078

Abstract: A prefetch input write driver for a random access memory (RAM) and a RAM including the prefetch input write driver. The prefetch input write driver is especially for a synchronous dynamic RAM (SDRAM). The prefetch input write driver includes a data input stage receiving data, an enable stage receiving a corresponding data enable, and a write driver providing received data to a memory array in response to a write signal and the corresponding enable stage state. The data stage and the enable stage may each include two or more series connected three state drivers and a latch at the output of each three state driver. As data passes through the data stage a corresponding enable state is passed through the enable stage. Data is passed to the RAM array if the enable state indicates that data in the data stage is to be written into the array.

Abstract translation: 用于随机存取存储器（RAM）的预取输入写入驱动器和包括预取输入写入驱动器的RAM。 预取输入写入驱动器特别适用于同步动态RAM（SDRAM）。 预取输入写入驱动器包括数据输入级接收数据，使能级接收对应的数据使能，以及写入驱动器，响应于写入信号和相应的使能级状态向存储器阵列提供接收到的数据。 数据级和使能级可以各自包括两个或更多个串联连接的三状态驱动器和每个三状态驱动器的输出端的锁存器。 当数据通过数据阶段时，相应的使能状态通过使能阶段。 如果使能状态指示要将数据级中的数据写入阵列，则将数据传递到RAM阵列。

公开(公告)号：WO0201703A2

公开(公告)日：2002-01-03

申请号：PCT/US0120407

申请日：2001-06-26

Applicant: INFINEON TECHNOLOGIES CORP

Inventor： WEINFURTNER OLIVER ,  MUELLER GERHARD

IPC: G11C5/14 ,  G11C17/18 ,  H02M3/00

CPC classification number: G11C17/18 ,  G11C5/145

Abstract: A voltage pump system for programming fuses on a semiconductor chip, in accordance with the present invention, includes a first pump system (12) employing a supply voltage (VDD) of the semiconductor chip as an input. The first pump system supplies an output voltage (VPP) higher than the supply voltage on a first output line (16) without raising the supply voltage of the semiconductor chip. A second pump system (20) includes an input connected to the first output. The second pump system supplies an output voltage (VFuse) sufficient for programming electrical fuses on the semiconductor chip.

Abstract translation: 根据本发明的用于在半导体芯片上编程熔丝的电压泵系统包括采用半导体芯片的电源电压（VDD）作为输入的第一泵系统（12）。 第一泵系统在不提高半导体芯片的电源电压的情况下提供高于第一输出线（16）上的电源电压的输出电压（VPP）。 第二泵系统（20）包括连接到第一输出的输入。 第二个泵系统提供足以在半导体芯片上编程电气保险丝的输出电压（VFuse）。

公开(公告)号：WO0126139A3

公开(公告)日：2001-10-18

申请号：PCT/US0027216

申请日：2000-10-02

Applicant: INFINEON TECHNOLOGIES CORP

Inventor： SCHNABEL RAINER FLORIAN ,  GRUENING ULRIKE ,  RUPP THOMAS ,  MUELLER GERHARD

IPC: G11C5/06 ,  G11C7/18 ,  G11C11/4097 ,  H01L21/285 ,  H01L21/60 ,  H01L21/768 ,  H01L21/8242 ,  H01L27/105 ,  H01L27/108

CPC classification number: H01L27/10885 ,  G11C5/063 ,  G11C7/18 ,  G11C11/4097 ,  H01L21/28525 ,  H01L21/76807 ,  H01L21/76897 ,  H01L27/105 ,  H01L27/10888 ,  H01L27/10894

Abstract: A method for fabricating a semiconductor memory with a split level folded bitline structure consisting of three contact levels, in accordance with the present invention, includes forming gate structures (204) for transistors in an array region (212) and a support region (214) of a substrate (202). First contacts (222) are formed down to diffusion regions between the gate structures in the array region. The first contacts have a height which is substantially the same for all first contacts in the array region. Second contacts (232) are formed between first level bitlines (234) in the array region and a first portion of the first contacts, while forming second contacts (236 and 260) to a first metal layer (233, 264) from the gate structures (204) and diffusion regions (262) in the support region. Third contacts (246) are formed between second level bitlines in the array region and a second portion of the first contacts, while forming third contacts to a second metal layer (251, 268) from the first metal layer in the support region.

Abstract translation: 根据本发明，制造具有由三个接触电平构成的分裂电平折叠位线结构的半导体存储器的方法包括：在阵列区域（212）和支撑区域（214）中形成用于晶体管的栅极结构（204） 的衬底（202）。 第一触点（222）形成在阵列区域中的栅极结构之间的扩散区域。 第一触点具有与阵列区域中的所有第一触点基本相同的高度。 第二触点（232）形成在阵列区域中的第一级位线（234）和第一触点的第一部分之间，同时从栅极结构形成第二触点（236和260）到第一金属层（233,264） （204）和扩散区（262）。 第三触点（246）形成在阵列区域中的第二电平位线和第一触点的第二部分之间，同时从支撑区域中的第一金属层形成第三触点到第二金属层（251,268）。