公开(公告)号：JP2000223668A

公开(公告)日：2000-08-11

申请号：JP2000022737

申请日：2000-01-31

Applicant: INFINEON TECHNOLOGIES CORP

Inventor： GRUENING ULRIKE ,  TOBBEN DIRK ,  SPINDLER OSWALD ,  BEINTNER JOCHEN ,  LEE GILL ,  GABRIC ZVONIMIR

IPC: H01L27/108 ,  H01L21/31 ,  H01L21/316 ,  H01L21/8242

Abstract: PROBLEM TO BE SOLVED: To control the thickness of an insulation layer at a trench by growing an oxide deposition layer selectively at high rate above a conductive material and then removing the oxide deposition layer selectively except a part touching the conductive material in order to form an insulation layer on the conductive material in the trench. SOLUTION: A pad stack 16 is formed by laminating a pad oxide layer 18 and a pad nitride layer 20 sequentially on a substrate 12 and a deep trench 14 is made through the stack 16. After the trench 14 is filled with a conductive filler 24 to leave a recess 26, a nitride liner 36 is deposited on the inside of the recess to cover the pad stack 16. Subsequently, the nitride liner 36 is removed from the entire surface except for the side-wall of the trench 14 and an oxide deposition layer 40 is grown selectively at high rate. Thereafter, the oxide deposition layer 40 is removed except a part touching the conductive filler 24 in order to form an insulation layer 44 on the conductive filler 24.

公开(公告)号：WO0227777A3

公开(公告)日：2002-08-29

申请号：PCT/US0126999

申请日：2001-08-30

Applicant: INFINEON TECHNOLOGIES CORP

Inventor： LEE GILL

IPC: H01L21/312 ,  H01L21/316

CPC classification number: H01L21/02126 ,  H01L21/02167 ,  H01L21/02211 ,  H01L21/02274 ,  H01L21/02304 ,  H01L21/02323 ,  H01L21/02337 ,  H01L21/02348 ,  H01L21/02362 ,  H01L21/3122

Abstract: An integrated circuit, and method of forming thereof, in which a CVD photoresist (e.g., PPMS) is formed on a substrate (e.g., silicon 200), patterned and converted into silicon oxide, and is left on the substrate to function as a silicon oxide layer (e.g., PPMSO 204). A high quality cap layer (e.g., PECVD silicon oxide 206) may then be formed over the lower quality silicon oxide layer utilizing a maskless etch process. A high quality silicon oxide layer may be formed on the substrate prior to formation of the CVD photoresist layer to provide a buffer underneath the lower quality silicon oxide. Because etch selectivity is generally not required for the photoresist layer, a thinner photoresist may be used than that of prior art techniques, permitting a larger lithographic process window, increased depth of focus, and a more robust process.

Abstract translation: 一种集成电路及其形成方法，其中在基板（例如，硅200）上形成CVD光致抗蚀剂（例如，PPMS），被图案化并转换成氧化硅，并留在基板上起硅的作用 氧化物层（例如，PPMSO 204）。 然后可以使用无掩模蚀刻工艺在较低质量的氧化硅层上形成高质量的覆盖层（例如，PECVD氧化硅206）。 在形成CVD光致抗蚀剂层之前，可以在衬底上形成高质量的氧化硅层，以在较低质量的氧化硅之下提供缓冲。 由于光致抗蚀剂层通常不需要蚀刻选择性，因此可以使用比现有技术更薄的光致抗蚀剂，允许更大的光刻工艺窗口，增加焦深和更坚固的工艺。