公开(公告)号：JP2001044384A

公开(公告)日：2001-02-16

申请号：JP2000220682

申请日：2000-07-21

Applicant: IBM ,  INFINEON TECHNOLOGIES CORP

Inventor： GRUENING ULRIKE ,  RADENS CARL J ,  TOBBEN DIRK

IPC: H01L27/108 ,  H01L21/76 ,  H01L21/8242

Abstract: PROBLEM TO BE SOLVED: To reduce a method for forming an embedded plate diffusion region in a deep trench storage capacitor by filling a non-photosensitive underfill material into the lower region of a trench before forming a collar at the upper region of the trench. SOLUTION: A trench 10 is covered with a thin barrier film 30, and a non- photosensitive underfill 16 is filled into the lower region of the trench 10. Then, the barrier film 30 is eliminated by an upper region 223 of the trench 10 by chemical etching using wet solution or the like. Also, the underfill 16 masks a lower region, 24 while the barrier film 30 at the upper region 22 is being removed. Then, the underfill 16 is removed from a lower region by stripping or the like by a chemical containing HF, and a collar 32 is formed at the upper region 22 by thermal oxidation growth or the like by the local oxidation process.

公开(公告)号：JP2000311991A

公开(公告)日：2000-11-07

申请号：JP2000080366

申请日：2000-03-22

Applicant: INFINEON TECHNOLOGIES CORP

Inventor： TOBBEN DIRK ,  ALSMEIER JOHANN

IPC: H01L27/108 ,  H01L21/8242

Abstract: PROBLEM TO BE SOLVED: To obtain a method of forming a DRAM on a silicon chip, where an NMOSFET of a memory cell is provided in the center region of the silicon chip, a CMOSFET of a support circuit is provided in the peripheral region of the silicon chip. SOLUTION: A support circuit 100B is masked with an SiO2 film 20, and a polyside film 22 in a memory 100A is doped with N-type impurities. An SiN cap layer 26 is deposited thereon and covered with a patterned mask, the laminate is successively etched up to a gate insulating oxide film 12, a substrate 10 is doped with N-type impurities, and the source and drain region 32 of the memory 100A are formed. A sidewall dielectric spacer 34 is formed, and after an NMOSFET memory is nearly completed, a CMOSFET is formed in the supper circuit 100B.

公开(公告)号：JP2000223668A

公开(公告)日：2000-08-11

申请号：JP2000022737

申请日：2000-01-31

Applicant: INFINEON TECHNOLOGIES CORP

Inventor： GRUENING ULRIKE ,  TOBBEN DIRK ,  SPINDLER OSWALD ,  BEINTNER JOCHEN ,  LEE GILL ,  GABRIC ZVONIMIR

IPC: H01L27/108 ,  H01L21/31 ,  H01L21/316 ,  H01L21/8242

Abstract: PROBLEM TO BE SOLVED: To control the thickness of an insulation layer at a trench by growing an oxide deposition layer selectively at high rate above a conductive material and then removing the oxide deposition layer selectively except a part touching the conductive material in order to form an insulation layer on the conductive material in the trench. SOLUTION: A pad stack 16 is formed by laminating a pad oxide layer 18 and a pad nitride layer 20 sequentially on a substrate 12 and a deep trench 14 is made through the stack 16. After the trench 14 is filled with a conductive filler 24 to leave a recess 26, a nitride liner 36 is deposited on the inside of the recess to cover the pad stack 16. Subsequently, the nitride liner 36 is removed from the entire surface except for the side-wall of the trench 14 and an oxide deposition layer 40 is grown selectively at high rate. Thereafter, the oxide deposition layer 40 is removed except a part touching the conductive filler 24 in order to form an insulation layer 44 on the conductive filler 24.

公开(公告)号：DE60036305D1

公开(公告)日：2007-10-18

申请号：DE60036305

申请日：2000-10-04

Applicant: INFINEON TECHNOLOGIES CORP ,  IBM

Inventor： TOBBEN DIRK ,  GAMBINO JEFFREY

IPC: H01L21/768 ,  H01L23/522

Abstract: A method for connecting metal structures with self-aligned metal caps, in accordance with the invention, includes providing a metal structure in a first dielectric layer. The metal structure and the first dielectric layer share a substantially planar surface. A cap metal is selectively depositing on the metal structure such that the cap metal is deposited only on the metal structure. A second dielectric layer is formed over the cap metal. The second dielectric layer is opened to form a via terminating in the cap metal. A conductive material is deposited in the via to provide a contact to the metal structure through the cap metal.

公开(公告)号：HK1032292A1

公开(公告)日：2001-07-13

申请号：HK01102673

申请日：2001-04-17

Applicant: IBM ,  INFINEON TECHNOLOGIES CORP

Inventor： GRUENING ULRIKE ,  RADENS CARL J ,  TOBBEN DIRK

IPC: H01L21/76 ,  H01L27/108 ,  H01L21/8242 ,  H01L

Abstract: A process for manufacturing a deep trench capacitor in a trench (10). The capacitor comprises a collar (18) in an upper region of the trench and a buried plate (26) in a lower region of the trench. The improvement comprises, before forming the collar in the trench upper region, filling the trench lower region with a non-photosensitive underfill material (16) such as spin-on-glass. The process may comprise the steps of (a) forming a deep trench in a substrate; (b) filling the trench lower region with an underfill material; (c) forming a collar in the trench upper region; (d) removing the underfill; and (e) forming a buried plate in the trench lower region.