公开(公告)号：JP2001358229A

公开(公告)日：2001-12-26

申请号：JP2001134513

申请日：2001-05-01

Applicant: IBM ,  INFINEON TECHNOLOGIES CORP

Inventor： YUN YUU WAN ,  JAMMY RAJARAO ,  KIMBALL LEE J ,  KOTECKI DAVID E ,  LIAN JENNY ,  CHENTEIN RIN ,  MILLER JOHN A ,  NAGEL NICHOLAS ,  SHEN HUA ,  WILDMAN HORATIO S

IPC: H01L27/108 ,  H01L21/02 ,  H01L21/8242

Abstract: PROBLEM TO BE SOLVED: To provide a recessed electrode structure which interrupts the crystal grain boundary of an electrode and blocks the diffusion from the side wall. SOLUTION: The capacitor structure comprises an upper platinum electrode, a lower electrode and an insulator on the side wall of the electrode, and the lower electrode has a first recessed portion deposited to the insulator on its side wall and a second insulator portion deposited thereto.

公开(公告)号：JP2000323685A

公开(公告)日：2000-11-24

申请号：JP2000087033

申请日：2000-03-27

Applicant: INFINEON TECHNOLOGIES CORP

Inventor： LIAN JENNY ,  GERHARD KUNKEL

IPC: H01L27/105 ,  H01L21/02 ,  H01L21/768 ,  H01L21/8242 ,  H01L21/8246 ,  H01L27/108 ,  H01L27/10

Abstract: PROBLEM TO BE SOLVED: To obtain a method of manufacturing in which the source/drain region of an FET and a capacitor lower electrode are connected in small resistance without diffusion barrier in a memory cell provided with a stacked capacitor on a MOS field effect transistor (MOSFET). SOLUTION: A polysilicon plug 12 passing through a silicon oxide layer 14 on a silicon chip and connected in correspondence with a source/drain region of an FET is formed and a platinum layer is etched with a dielectric layer 16 as stopper to form a conductor 20. Then a high-dielectric layer 22, a capacitor upper electrode 24 and a dielectric layer 25 such as TEOS are layered, etching is carried out up to the polysilicon plug 12 leaving platinum conductors 20 to form an opening 32, a liner film 28 is formed, a conductive contact 30 is formed being insulated from the upper electrode 24, and the upper part is filled with TEOS 32 or the like.

公开(公告)号：WO03003475A2

公开(公告)日：2003-01-09

申请号：PCT/US0219094

申请日：2002-06-17

Applicant: INFINEON TECHNOLOGIES CORP

Inventor： LIAN JENNY ,  NING XIAN J

IPC: H01L21/02 ,  H01L21/314 ,  H01L21/316 ,  H01L21/768 ,  H01L27/06 ,  H01L29/92

CPC classification number: H01L28/55 ,  H01L21/31691 ,  H01L21/76838 ,  H01L27/0629 ,  H01L28/60

Abstract: A method of forming a metal-insulator-metal capacitor (see e.g., Figure 1) in a back end of line structure comprises forming a metal bottom plate 16 in a first metalization layer 14, sputter depositing a high dielectric constant material 18 over the bottom plate 16, and forming a metal top plate 20 in a second metalization layer 22. The metal bottom plate 16 and metal top plate 22 are formed in consecutive metalization layers 14 and 22 in which interconnect structures 12 and 24 are also formed.

Abstract translation: 在线结构的后端中形成金属 - 绝缘体 - 金属电容器（参见例如图1）的方法包括在第一金属化层14中形成金属底板16，在底部溅射沉积高介电常数材料18 板16，并且在第二金属化层22中形成金属顶板20.金属底板16和金属顶板22形成在连续的金属化层14和22中，其中还形成有互连结构12和24。