公开(公告)号：JP2001005660A

公开(公告)日：2001-01-12

申请号：JP2000157106

申请日：2000-05-26

Applicant: INFINEON TECHNOLOGIES CORP

Inventor： SINGH BALRAJ ,  MATTELA VENKAT ,  CHESTERS ERIC ,  FLECK ROD G

IPC: G06F12/08 ,  G06F9/30 ,  G06F9/38

Abstract: PROBLEM TO BE SOLVED: To make increasable the instruction issue bus bandwidth without increasing the size of a cache memory by selectively storing instructions in the cache memory related to a corresponding function unit. SOLUTION: A 1st instruction is fetched from a memory and it is judged whether its PS matches with one of entries of a tag PC cache (S502, 504). When the tag PC of the fetched instruction matches with one of the entries of one of tag PC caches, the PC of the fetched instruction is updated into a matching target PC specified in a cache memory (S504, 514). When a target instruction is stored in the fetched instruction, the target instruction is fetched from a program memory (S516, 518), but when the target instruction is stored in the fetched instruction, the target instruction is not requested of a programming memory; and a target operation code is injected into a target function unit (S520) in either case together with the target instruction.

公开(公告)号：DE10025955C2

公开(公告)日：2002-03-28

申请号：DE10025955

申请日：2000-05-26

Applicant: INFINEON TECHNOLOGIES CORP

Inventor： SINGH BALRAJ ,  MATTELA VENKAT ,  GRUBERT ANDREAS

IPC: G06F9/32 ,  G06F9/38

公开(公告)号：DE69809450D1

公开(公告)日：2002-12-19

申请号：DE69809450

申请日：1998-09-04

Applicant: INFINEON TECHNOLOGIES CORP

Inventor： FLECK H ,  MATTELA VENKAT ,  CHESTERS ERIC ,  AFSAR MUHAMMAD

IPC: G06F9/32 ,  G06F9/38

Abstract: The data processing device according to the invention comprises an instruction providing unit having an input and an output, a pipeline unit for processing data having input and output stages, a loop pipeline unit for processing a loop instruction having input and output stages, said input stages of said pipeline units being coupled to said output of said instruction providing unit, said instruction providing unit providing data for said pipelines, and said pipeline units processing said data independently.

公开(公告)号：DE10025952A1

公开(公告)日：2001-05-31

申请号：DE10025952

申请日：2000-05-26

Applicant: INFINEON TECHNOLOGIES CORP

Inventor： SINGH BALRAJ ,  GAUTHO MANUEL O ,  MATTELA VENKAT

IPC: G06F9/38 ,  G06F12/04 ,  G06F12/08

Abstract: The cache memory has four memory banks (1-4) with 16 bit outputs connected to a ring counter (5) that transfers values into a buffer (12). Control units (6,9) provide read and write signals (10,11) for the ring counter and the buffer. Coupled to the buffer is a multiplexing system (14,15)

公开(公告)号：DE10025955A1

公开(公告)日：2000-12-07

申请号：DE10025955

申请日：2000-05-26

Applicant: INFINEON TECHNOLOGIES CORP

Inventor： SINGH BALRAJ ,  MATTELA VENKAT ,  GRUBERT ANDREAS

IPC: G06F9/32 ,  G06F9/38

公开(公告)号：DE10025952B4

公开(公告)日：2004-07-29

申请号：DE10025952

申请日：2000-05-26

Applicant: INFINEON TECHNOLOGIES CORP

Inventor： SINGH BALRAJ ,  GAUTHO MANUEL O ,  MATTELA VENKAT

IPC: G06F9/38 ,  G06F12/04 ,  G06F12/08

Abstract: A data processing unit having superscalar structure able to execute a plurality of instructions in parallel includes a memory for storing the instructions having a plurality of n-bit input/output ports, an instruction fetch unit, a coupling unit for coupling said memory with the instruction fetch unit, and an instruction stream request control unit for addressing the mmory to provide an instruction stream at its output ports. The coupling unit includes a shifter having an input and an output and a control input, the input being coupled with the output ports of the memory, the output being coupled with the instruction fetch unit, and the control input being coupled with the instruction stream request control unit. The instruction fetch unit has a register for storing said instruction stream and a shifter to shift the content of the register.

公开(公告)号：DE69809450T2

公开(公告)日：2003-07-03

申请号：DE69809450

申请日：1998-09-04

Applicant: INFINEON TECHNOLOGIES CORP

Inventor： FLECK H ,  MATTELA VENKAT ,  CHESTERS ERIC ,  AFSAR MUHAMMAD

IPC: G06F9/32 ,  G06F9/38

Abstract: The data processing device according to the invention comprises an instruction providing unit having an input and an output, a pipeline unit for processing data having input and output stages, a loop pipeline unit for processing a loop instruction having input and output stages, said input stages of said pipeline units being coupled to said output of said instruction providing unit, said instruction providing unit providing data for said pipelines, and said pipeline units processing said data independently.

公开(公告)号：DE10026017A1

公开(公告)日：2000-12-28

申请号：DE10026017

申请日：2000-05-25

Applicant: INFINEON TECHNOLOGIES CORP

Inventor： SINGH BALRAJ ,  MATTELA VENKAT

IPC: G06F9/38 ,  G06F12/08

Abstract: The method involves using a pre-polled buffer (4,5) contg. pre-polled commands and additional information about the validity and size of the buffer. If the buffer contains invalid data then a command sequence is called up and stored in the buffer, set as valid, data are extracted and the size of the buffer data reduced accordingly, then the validity data are set as invalid after all commands have been extracted. If the buffer contains valid data then commands are output, data are extracted and the size of the buffer data reduced accordingly, then the validity data are set as invalid. An Independent claim is also included for an arrangement for generating addressed commands from a command sequence in a memory unit for implementation in a pipeline microprocessor with a pre-polling buffer.

公开(公告)号：DE10026017B4

公开(公告)日：2007-02-08

申请号：DE10026017

申请日：2000-05-25

Applicant: INFINEON TECHNOLOGIES CORP

Inventor： SINGH BALRAJ ,  MATTELA VENKAT

IPC: G06F9/38 ,  G06F13/00

Abstract: A method and apparatus for providing a plurality of aligned instructions from an instruction stream provided by a memory unit for execution within a pipelined microprocessor is described. The microprocessor comprises a prefetch buffer, whereby the prefetch buffer stores prefetched instructions and additional information about the validity and size of the prefetch buffer. The method and apparatus use the prefetch buffer to buffer a part of an instruction stream. The actually aligned instruction stream is issued from the prefetch buffer or directly by instructions fetched from the memory, or from a combination of prefetched instructions and actually fetched instructions.