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    METHOD AND DEVICE FOR REDUCING INSTRUCTION TRANSACTION IN MICROPROCESSOR
    1.
    发明专利
    METHOD AND DEVICE FOR REDUCING INSTRUCTION TRANSACTION IN MICROPROCESSOR 失效

    公开(公告)号：JP2001005660A

    公开(公告)日：2001-01-12

    申请号：JP2000157106

    申请日：2000-05-26

    Applicant: INFINEON TECHNOLOGIES CORP

    Inventor： SINGH BALRAJ ,  MATTELA VENKAT ,  CHESTERS ERIC ,  FLECK ROD G

    IPC: G06F12/08 ,  G06F9/30 ,  G06F9/38

    Abstract: PROBLEM TO BE SOLVED: To make increasable the instruction issue bus bandwidth without increasing the size of a cache memory by selectively storing instructions in the cache memory related to a corresponding function unit. SOLUTION: A 1st instruction is fetched from a memory and it is judged whether its PS matches with one of entries of a tag PC cache (S502, 504). When the tag PC of the fetched instruction matches with one of the entries of one of tag PC caches, the PC of the fetched instruction is updated into a matching target PC specified in a cache memory (S504, 514). When a target instruction is stored in the fetched instruction, the target instruction is fetched from a program memory (S516, 518), but when the target instruction is stored in the fetched instruction, the target instruction is not requested of a programming memory; and a target operation code is injected into a target function unit (S520) in either case together with the target instruction.

    4.
    发明专利
    未知

    公开(公告)号：DE69809450D1

    公开(公告)日：2002-12-19

    申请号：DE69809450

    申请日：1998-09-04

    Applicant: INFINEON TECHNOLOGIES CORP

    Inventor： FLECK H ,  MATTELA VENKAT ,  CHESTERS ERIC ,  AFSAR MUHAMMAD

    IPC: G06F9/32 ,  G06F9/38

    Abstract: The data processing device according to the invention comprises an instruction providing unit having an input and an output, a pipeline unit for processing data having input and output stages, a loop pipeline unit for processing a loop instruction having input and output stages, said input stages of said pipeline units being coupled to said output of said instruction providing unit, said instruction providing unit providing data for said pipelines, and said pipeline units processing said data independently.

    8.
    发明专利
    未知

    公开(公告)号：DE69809450T2

    公开(公告)日：2003-07-03

    申请号：DE69809450

    申请日：1998-09-04

    Applicant: INFINEON TECHNOLOGIES CORP

    Inventor： FLECK H ,  MATTELA VENKAT ,  CHESTERS ERIC ,  AFSAR MUHAMMAD

    IPC: G06F9/32 ,  G06F9/38

    Abstract: The data processing device according to the invention comprises an instruction providing unit having an input and an output, a pipeline unit for processing data having input and output stages, a loop pipeline unit for processing a loop instruction having input and output stages, said input stages of said pipeline units being coupled to said output of said instruction providing unit, said instruction providing unit providing data for said pipelines, and said pipeline units processing said data independently.

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