公开(公告)号：WO0203466A3

公开(公告)日：2002-05-30

申请号：PCT/US0120914

申请日：2001-06-29

Applicant: INFINEON TECHNOLOGIES CORP ,  IBM

Inventor： COSTRINI GREGORY ,  SEITZ MIHEL

IPC: H01L21/60 ,  H01L27/105 ,  H01L21/8234

CPC classification number: H01L21/76897

Abstract: A method of fabricating a semiconductor device in which the bitlines and the bitline contacts are fabricated utilizing a single masking step in which line-space resist patterns are employed in defining the regions for the bitlines and the bitline contacts. The method utilizes a first line-space resist pattern and a second line-space resist pattern which is perpendicularly aligned to the first line-space resist pattern to form bitlines that are self-aligned to the bitline contacts.

Abstract translation: 一种制造半导体器件的方法，其中利用单个掩蔽步骤制造位线和位线接触，其中线间隔抗蚀剂图案用于限定位线和位线接触的区域。 该方法利用与第一线间隔抗蚀剂图案垂直对准的第一线间隔抗蚀剂图案和第二线间隔抗蚀剂图案，以形成与位线接触自对准的位线。

公开(公告)号：DE602006006088D1

公开(公告)日：2009-05-14

申请号：DE602006006088

申请日：2006-07-25

Applicant: IBM

Inventor： DORIS BRUCE ,  COSTRINI GREGORY ,  GLUSCHENKOV OLEG ,  LEONG MEIKEI ,  SEONG NAKGEUON

IPC: H01L27/11 ,  H01L21/8244

Abstract: The present invention relates to a semiconductor device structure that includes at least one SRAM cell formed in a substrate. Such SRAM cell comprises two pull-up transistors, two pull-down transistors, and two pass-gate transistors. The pull-down transistors and the pass-gate transistors are substantially similar in channel widths and have substantially similar source-drain doping concentrations, while the SRAM cell has a beta ratio of at least 1.5. The substrate preferably comprises a hybrid substrate with at two isolated sets of regions, while carrier mobility in these two sets of regions differentiates by a factor of at least about 1.5. More preferably, the pull-down transistors of the SRAM cell are formed in one set of regions, and the pass-gate transistors are formed in the other set of regions, so that current flow in the pull-down transistors is larger than that in the pass-gate transistors.

公开(公告)号：AT427563T

公开(公告)日：2009-04-15

申请号：AT06777968

申请日：2006-07-25

Applicant: IBM

Inventor： DORIS BRUCE ,  COSTRINI GREGORY ,  GLUSCHENKOV OLEG ,  LEONG MEIKEI ,  SEONG NAKGEUON

IPC: H01L27/11 ,  H01L21/8244

Abstract: The present invention relates to a semiconductor device structure that includes at least one SRAM cell formed in a substrate. Such SRAM cell comprises two pull-up transistors, two pull-down transistors, and two pass-gate transistors. The pull-down transistors and the pass-gate transistors are substantially similar in channel widths and have substantially similar source-drain doping concentrations, while the SRAM cell has a beta ratio of at least 1.5. The substrate preferably comprises a hybrid substrate with at two isolated sets of regions, while carrier mobility in these two sets of regions differentiates by a factor of at least about 1.5. More preferably, the pull-down transistors of the SRAM cell are formed in one set of regions, and the pass-gate transistors are formed in the other set of regions, so that current flow in the pull-down transistors is larger than that in the pass-gate transistors.

公开(公告)号：DE69009844T2

公开(公告)日：1995-01-05

申请号：DE69009844

申请日：1990-03-13

Applicant: IBM

Inventor： COSTRINI GREGORY ,  JAMBOTKAR CHAKRAPANI GAJANAN

IPC: H01L27/15 ,  G02B6/124 ,  H01S5/00 ,  H01S5/02 ,  H01S5/026 ,  H01S5/028 ,  H01S5/227 ,  H01L33/00 ,  H01S3/025

Abstract: A planar process for fabricating an optoelectronic integrated circuit device is described. The process includes the in situ formation of laser diode mirror facets comprising the steps of providing a semi-insulating gallium arsenide substrate (2) having thereon layers of n-doped gallium arsenide (4), n-doped aluminum gallium arsenide (6), and undoped gallium arsenide (8); patterning and etching the undoped gallium arsenide layer (8) into a mandrel (9) having substantially vertical walls (44); establishing insulator sidewalls (14) on the vertical walls (44); removing the mandrel (9), thereby exposing the inner walls (45) of the insulator sidewalls (14) and leaving the insulator sidewalls (14) self-standing; removing the aluminum gallium arsenide (6) using the insulator sidewall (14) as a mask; and forming a laser diode within the region between the insulator sidewalls (14) and creating the mirror facets (13) with the inner walls (45) of the insulator sidewalls (14). Mirror facets (13) formed in accordance with this process are substantially free of contaminants. The process is suitable for high level of monolithic integration, including the formation of other optical devices, such as waveguides, driver circuits, logic and other electronic circuits.

公开(公告)号：DE69009844D1

公开(公告)日：1994-07-21

申请号：DE69009844

申请日：1990-03-13

Applicant: IBM

Inventor： COSTRINI GREGORY ,  JAMBOTKAR CHAKRAPANI GAJANAN

IPC: H01L27/15 ,  G02B6/124 ,  H01S5/00 ,  H01S5/02 ,  H01S5/026 ,  H01S5/028 ,  H01S5/227 ,  H01L33/00 ,  H01S3/025

Abstract: A planar process for fabricating an optoelectronic integrated circuit device is described. The process includes the in situ formation of laser diode mirror facets comprising the steps of providing a semi-insulating gallium arsenide substrate (2) having thereon layers of n-doped gallium arsenide (4), n-doped aluminum gallium arsenide (6), and undoped gallium arsenide (8); patterning and etching the undoped gallium arsenide layer (8) into a mandrel (9) having substantially vertical walls (44); establishing insulator sidewalls (14) on the vertical walls (44); removing the mandrel (9), thereby exposing the inner walls (45) of the insulator sidewalls (14) and leaving the insulator sidewalls (14) self-standing; removing the aluminum gallium arsenide (6) using the insulator sidewall (14) as a mask; and forming a laser diode within the region between the insulator sidewalls (14) and creating the mirror facets (13) with the inner walls (45) of the insulator sidewalls (14). Mirror facets (13) formed in accordance with this process are substantially free of contaminants. The process is suitable for high level of monolithic integration, including the formation of other optical devices, such as waveguides, driver circuits, logic and other electronic circuits.