公开(公告)号：WO0231878A3

公开(公告)日：2002-10-31

申请号：PCT/US0126644

申请日：2001-08-24

Applicant: INFINEON TECHNOLOGIES CORP ,  IBM

Inventor： JAIPRAKASH VENKATACHALAN ,  MANDELMAN JACK ,  DIVAKARUNI RAMACHANDRAR ,  MALIK RAJEEV ,  SEITZ MIHEL

IPC: H01L21/8242

CPC classification number: H01L27/10861

Abstract: An array top oxide is protected in the manufacture of vertical metal oxide semiconductor field effect transistor (MOSFET) dynamic random access memory (DRAM) arrays by a protective etch stop layer (18) which protects the top oxide (16) and prevents word line to substrate shorts and/or leakage. Processing of a DRAM device containing vertical MOSFET arrays proceeds through planarization of the array gate conductor polysilicon (17) of the vertical MOSFET to the top surface of the top oxide (16). A thin polysilicon layer (18) is deposited over the planarized surface and an active area (AA) pad nitride and tetraethyl orthosilicate (TEOS) stack is deposited. The AA mask is used to open the pad layer to the silicon surface, and shallow trench isolation (STI) etching is used to form isolation trenches (20).

Abstract translation: 在通过保护顶部氧化物（16）的保护性蚀刻停止层（18）制造垂直金属氧化物半导体场效应晶体管（MOSFET）动态随机存取存储器（DRAM）阵列中的阵列顶部氧化物被保护，并且防止字线 衬底短路和/或泄漏。 包括垂直MOSFET阵列的DRAM器件的处理通过将垂直MOSFET的阵列栅极导体多晶硅（17）平坦化到顶部氧化物（16）的顶表面进行。 在平坦化表面上沉积薄多晶硅层（18），并沉积有源区（AA）衬垫氮化物和原硅酸四乙酯（TEOS）堆叠。 使用AA掩模将焊盘层打开到硅表面，并且使用浅沟槽隔离（STI）蚀刻来形成隔离沟槽（20）。

公开(公告)号：WO0203466A3

公开(公告)日：2002-05-30

申请号：PCT/US0120914

申请日：2001-06-29

Applicant: INFINEON TECHNOLOGIES CORP ,  IBM

Inventor： COSTRINI GREGORY ,  SEITZ MIHEL

IPC: H01L21/60 ,  H01L27/105 ,  H01L21/8234

CPC classification number: H01L21/76897

Abstract: A method of fabricating a semiconductor device in which the bitlines and the bitline contacts are fabricated utilizing a single masking step in which line-space resist patterns are employed in defining the regions for the bitlines and the bitline contacts. The method utilizes a first line-space resist pattern and a second line-space resist pattern which is perpendicularly aligned to the first line-space resist pattern to form bitlines that are self-aligned to the bitline contacts.

Abstract translation: 一种制造半导体器件的方法，其中利用单个掩蔽步骤制造位线和位线接触，其中线间隔抗蚀剂图案用于限定位线和位线接触的区域。 该方法利用与第一线间隔抗蚀剂图案垂直对准的第一线间隔抗蚀剂图案和第二线间隔抗蚀剂图案，以形成与位线接触自对准的位线。

公开(公告)号：WO0250896A3

公开(公告)日：2004-01-08

申请号：PCT/US0145196

申请日：2001-11-29

Applicant: INFINEON TECHNOLOGIES CORP

Inventor： SEITZ MIHEL ,  WISE MICHAEL L ,  DUBUC CHRISTIAN

IPC: H01L21/8242

CPC classification number: H01L27/10864 ,  H01L27/10876 ,  H01L27/10888 ,  H01L27/10891

Abstract: A Dynamic Random Access Memory is fabricated in a semiconductor body (12) of a first conductivity type in which there have been formed an array of memory cells which each include a trench capacitor and a vertical Insulated Gate Field Effect Transistor (IGFET). Each IGFET includes first (18) and second (19) output regions of a second opposite conductivity type and a gate (25) which is separated from a surface of the semiconductor body by a gate dielectric layer (21). A gate electrode (40b) connected to the gate (25) is formed using a Damascene process with insulating sidewall spacer regions (36) being formed before the gate electrode (25) is formed. Borderless contacts (56, 560), which are self aligned, are made to the first output regions (18) of each transistor using a Damascene process.

Abstract translation: 在第一导电类型的半导体本体（12）中制造动态随机存取存储器，其中已经形成了各自包括沟槽电容器和垂直绝缘栅场效应晶体管（IGFET）的存储单元阵列。 每个IGFET包括第二相对导电类型的第一（18）和第二（19）输出区和通过栅介质层（21）与半导体本体的表面分离的栅极（25）。 连接到栅极（25）的栅电极（40b）使用具有在形成栅电极（25）之前形成的绝缘侧壁间隔区（36）的镶嵌工艺形成。 使用大马士革过程对每个晶体管的第一输出区域（18）进行自对准的无边界触点（56,560）。

公开(公告)号：WO0201293A3

公开(公告)日：2002-08-15

申请号：PCT/US0120408

申请日：2001-06-26

Applicant: INFINEON TECHNOLOGIES CORP

Inventor： SEITZ MIHEL ,  KUNKEL GERHARD

IPC: G03F1/00 ,  G03F1/14

CPC classification number: G03F1/36

Abstract: A photomask for lithographic processing, in accordance with the present invention, includes a plurality of features (104) for providing an image pattern. The features are arranged in a column (106) on a mask substrate (101). Each feature is dimensioned to provide an individual image separate from all other images provided by the photomask when exposed to light. A line feature (110) is formed on the mask substrate and extends between and intersects with each of the plurality of features in the column. The line feature extends a length of images produced by the plurality of features arranged in the column when exposed to light wherein the images produced by each of the plurality of features and the line feature remain separate from each other.

Abstract translation: 根据本发明的用于光刻处理的光掩模包括用于提供图像图案的多个特征（104）。 这些特征被布置在掩模衬底（101）上的列（106）中。 每个特征的尺寸被设计成提供与暴露于光线时由光掩模提供的所有其他图像分离的单独图像。 线特征（110）形成在掩模基板上并且在列中的多个特征中的每个特征之间延伸并与之交叉。 当暴露于光线时，线条特征延伸由排列在列中的多个特征产生的图像的长度，其中由多个特征中的每一个和线条特征产生的图像保持彼此分离。

公开(公告)号：WO0225729A2

公开(公告)日：2002-03-28

申请号：PCT/US0126232

申请日：2001-08-22

Applicant: INFINEON TECHNOLOGIES CORP

Inventor： SEITZ MIHEL ,  KNORR ANDREAS ,  MCSTAY IRENE

IPC: H01L21/8242 ,  H01L21/20

CPC classification number: H01L27/10867 ,  H01L27/10864

Abstract: A high density plasma deposition process for eliminating or reducing a zipper-like profile of opened-up voids in a poly trench fill by controlling separation between a transfer gate and storage node in a vertical DRAM, comprising: etching a recess or trench into poly Si of a semiconductor chip; forming a pattern of SiN liner using a mask transfer process for formation of a single sided strap design; removing the SiN liner and etching adjacent collar oxide away from a top part of the trench; depositing a high density plasma (HDP) polysilicon layer in the trench by flowing either SiH4 or SiH4 + H2 in an inert ambient; employing a photores ist in the trench and removing the high density plasma polysilicon layer from a top surface of the semiconductor to avoid shorting in the gate conductor either by spinning on resist and subsequent chemical mechanical polishing or chemical mechanical downstream etchback of the polysilicon layer; and stripping the photoresist and depositing a top trench oxide by high density plasma.

Abstract translation: 一种高密度等离子体沉积工艺，用于通过控制垂直DRAM中的转移栅极和存储节点之间的分离来消除或减少多沟槽填充物中的开放空隙的拉链状轮廓，包括：将凹槽或沟槽蚀刻成多晶硅 的半导体芯片; 使用掩模转移工艺形成SiN衬垫的图案以形成单面带设计; 去除SiN衬垫并且蚀刻邻近的环氧化物远离沟槽的顶部; 通过在惰性环境中流过SiH4或SiH4 + H2，在沟槽中沉积高密度等离子体（HDP）多晶硅层; 在沟槽中采用光电池，并从半导体的顶表面去除高密度等离子体多晶硅层，以避免通过在抗蚀剂上旋转和随后的多晶硅层的化学机械抛光或化学机械下游回蚀而在栅极导体中短路; 并剥离光致抗蚀剂并通过高密度等离子体沉积顶部沟槽氧化物。

公开(公告)号：DE10228691A1

公开(公告)日：2003-03-13

申请号：DE10228691

申请日：2002-06-27

Applicant: INFINEON TECHNOLOGIES CORP

Inventor： KNORR ANDREAS ,  SEITZ MIHEL

IPC: H01L21/762 ,  H01L21/8242

Abstract: A method of providing isolation between element regions of a semiconductor memory device (200). Isolation trenches (211) are filled using several sequential anisotropic insulating material (216/226/230) HPD-CVD deposition processes, with each deposition process being followed by an isotropic etch back to remove the insulating material (216/226/230) from the isolation trench (211) sidewalls. A nitride liner (225) may be deposited after isolation trench (211) formation. A top portion of the nitride liner (225) may be removed prior to the deposition of the top insulating material (230) layer.

公开(公告)号：JP2004153250A

公开(公告)日：2004-05-27

申请号：JP2003339550

申请日：2003-09-30

Applicant: Internatl Business Mach Corp ,  インターナショナル・ビジネス・マシーンズ・コーポレーションInternational Business Maschines Corporation

Inventor： SEITZ MIHEL ,  CHUDZIK MICHAEL P ,  MANDELMAN JACK A

IPC: H01L27/108 ,  H01L21/329 ,  H01L21/8242 ,  H01L29/94

CPC classification number: H01L27/10867 ,  H01L29/66166 ,  H01L29/945

Abstract: PROBLEM TO BE SOLVED: To provide a memory cell in which leakage between a buried strap and a buried plate is reduced by decreasing or eliminating parasitic transistors between the buried strap and the buried plate in a trench capacitor storage cell, and to provide a method for forming it.
SOLUTION: A memory cell comprises a trench capacitor containing a trench silicon layer having an upper part and a lower part and the buried plate arranged at the lower part of the trench silicon layer while adjoining it; a FET array comprising a gate part, a drain part, a source part and the buried strap which is combined with one of the source part and the drain part and further combined with the upper part of the trench silicon layer; and a collar, arranged between the buried strap and the buried plate at the periphery of the upper part of the trench silicon layer, which has a reentrant bending part operable so as to decrease an electric field between the buried strap and the buried plate.
COPYRIGHT: (C)2004,JPO

公开(公告)号：DE10350703A1

公开(公告)日：2004-05-27

申请号：DE10350703

申请日：2003-10-30

Applicant: IBM ,  INFINEON TECHNOLOGIES AG

Inventor： MANDELMAN JACK A ,  CHUDZIK MICHAEL ,  SEITZ MIHEL

IPC: H01L27/108 ,  H01L21/329 ,  H01L21/8242 ,  H01L29/94

Abstract: A memory cell includes: a trench capacitor, including a trench silicon layer having an upper portion and a lower portion, and a buried plate disposed adjacent the lower portion of the trench silicon layer; an array FET having a gate portion, a drain portion, a source portion, and a buried strap coupled to one of the source and drain portions, the buried strap being in communication with the upper portion of the trench silicon layer; and a collar disposed about the upper portion of the trench silicon layer and between the buried strap and the buried plate, the collar including a re-entrant bend that is operable to decrease an electric field between the buried strap and the buried plate.

公开(公告)号：DE10350703B4

公开(公告)日：2009-04-02

申请号：DE10350703

申请日：2003-10-30

Applicant: IBM ,  QIMONDA AG

Inventor： MANDELMAN JACK A ,  CHUDZIK MICHAEL ,  SEITZ MIHEL

IPC: H01L21/8242 ,  H01L27/108 ,  H01L21/329 ,  H01L29/94

Abstract: A memory cell includes: a trench capacitor, including a trench silicon layer having an upper portion and a lower portion, and a buried plate disposed adjacent the lower portion of the trench silicon layer; an array FET having a gate portion, a drain portion, a source portion, and a buried strap coupled to one of the source and drain portions, the buried strap being in communication with the upper portion of the trench silicon layer; and a collar disposed about the upper portion of the trench silicon layer and between the buried strap and the buried plate, the collar including a re-entrant bend that is operable to decrease an electric field between the buried strap and the buried plate.