公开(公告)号：JP2000323684A

公开(公告)日：2000-11-24

申请号：JP2000085406

申请日：2000-03-24

Applicant: INFINEON TECHNOLOGIES CORP ,  IBM

Inventor： GRUENING ULRIKE ,  HALLE SCOTT ,  RADENS CARL J ,  JEFFREY J WERSER ,  BEINTNER JOCHEN ,  MANDELMAN JACK A ,  WITTMANN JUERGEN

IPC: H01L27/108 ,  H01L21/8242

Abstract: PROBLEM TO BE SOLVED: To form a trench capacitor in a semiconductor body. SOLUTION: A trench capacitor 10 and a MOS transistor 9 are provided in a substrate 16 to form a cell 8 of the DRAM, and the cell 8 is separated from adjacent cells by an STI region 28. The capacitor 10 is composed of an insulator 14 enveloping the trench and a first electrode 24 filled with polysilicon 12, is connected to the drain portion 72 through a buried electrode 22, and is insulated from a gate electrode 20 by a dielectric 23. A second electrode 25 is formed in its bottom portion through an insulator 14. A transistor 9 has N-type drain 72 and source 71 in an upper active region 11 of the substrate 16 and operates with a p well as channel.

公开(公告)号：JP2000196069A

公开(公告)日：2000-07-14

申请号：JP36899699

申请日：1999-12-27

Applicant: INFINEON TECHNOLOGIES CORP ,  IBM

Inventor： AKATSU HIROYUKI ,  YUUJUN RII ,  BEINTNER JOCHEN

IPC: H01L29/78 ,  H01L21/336 ,  H01L21/8234 ,  H01L29/10

Abstract: PROBLEM TO BE SOLVED: To form a buried layer self-aligned with a gate and a channel by solving the problem when introducing a buried layer, which is heavily-doped with impurities, having an opposite conductivity which is opposite to the conductivity of the source and the drain, along the width of a channel. SOLUTION: This transistor has a dielectric layer, a gate conductor, and a buried region, and the dielectric layer is arranged to be fit for use as the gate dielectric above the semiconductor body 10 between a first region and a second region, and the gate conductor is so arranged above the dielectric layer as to be used as the gate 18, and the buried region is of first conductivity and moreover has impurity concentration higher than the semiconductor body 10, and it is arranged basically apart from the surface of the semiconductor body 10, between the first region and the second region, and the buried region is aligned with the gate conductor.

公开(公告)号：WO0199164A3

公开(公告)日：2002-07-25

申请号：PCT/US0119660

申请日：2001-06-20

Applicant: INFINEON TECHNOLOGIES CORP ,  IBM

Inventor： LEE GILL YONG ,  HALLE SCOTT D ,  BEINTNER JOCHEN

IPC: G03F7/09 ,  H01L21/027 ,  H01L21/311 ,  H01L21/314 ,  H01L21/8242 ,  H01L21/033 ,  H01L21/32

CPC classification number: H01L21/0276 ,  G03F7/091 ,  H01L21/31116 ,  H01L21/31133 ,  H01L21/3145 ,  H01L27/10861

Abstract: In accordance with the present invention, a method for employing and removing inorganic anti-reflection coatings, includes the steps of providing a first dielectric layer (122) on a semiconductor device (110) structure to be processed, the first dielectric layer being selectively removable relative to the semiconductor device structure, and forming an inorganic dielectric anti-reflection coating (DARC) (124) on the first dielectric layer, the DARC being selectively removable relative to the first dielectric layer. A resist layer (130) is patterned on the DARC. The resist is selectively removable relative to the DARC. The semiconductor device structure is etched, and the resist layer, the DARC and the first dielectric layer are selectively removed.

Abstract translation: 根据本发明，一种采用和去除无机抗反射涂层的方法包括以下步骤：在要加工的半导体器件（110）结构上提供第一介电层（122），所述第一介电层可选择性地可移除 相对于半导体器件结构，以及在第一电介质层上形成无机介电抗反射涂层（DARC）（124），所述DARC可相对于第一介电层选择性地去除。 抗蚀剂层（130）在DARC上被图案化。 抗蚀剂相对于DARC有选择性地可去除。 蚀刻半导体器件结构，并且选择性地去除抗蚀剂层，DARC和第一介电层。

公开(公告)号：DE10226568A1

公开(公告)日：2003-02-06

申请号：DE10226568

申请日：2002-06-14

Applicant: INFINEON TECHNOLOGIES CORP ,  IBM

Inventor： MALIK RAJEEB ,  NESBIT LARRY ,  BEINTNER JOCHEN ,  DIVAKARUNI RAMA

IPC: H01L21/762 ,  H01L21/8242 ,  H01L27/108

公开(公告)号：JP2000223668A

公开(公告)日：2000-08-11

申请号：JP2000022737

申请日：2000-01-31

Applicant: INFINEON TECHNOLOGIES CORP

Inventor： GRUENING ULRIKE ,  TOBBEN DIRK ,  SPINDLER OSWALD ,  BEINTNER JOCHEN ,  LEE GILL ,  GABRIC ZVONIMIR

IPC: H01L27/108 ,  H01L21/31 ,  H01L21/316 ,  H01L21/8242

Abstract: PROBLEM TO BE SOLVED: To control the thickness of an insulation layer at a trench by growing an oxide deposition layer selectively at high rate above a conductive material and then removing the oxide deposition layer selectively except a part touching the conductive material in order to form an insulation layer on the conductive material in the trench. SOLUTION: A pad stack 16 is formed by laminating a pad oxide layer 18 and a pad nitride layer 20 sequentially on a substrate 12 and a deep trench 14 is made through the stack 16. After the trench 14 is filled with a conductive filler 24 to leave a recess 26, a nitride liner 36 is deposited on the inside of the recess to cover the pad stack 16. Subsequently, the nitride liner 36 is removed from the entire surface except for the side-wall of the trench 14 and an oxide deposition layer 40 is grown selectively at high rate. Thereafter, the oxide deposition layer 40 is removed except a part touching the conductive filler 24 in order to form an insulation layer 44 on the conductive filler 24.

公开(公告)号：WO0199158A2

公开(公告)日：2001-12-27

申请号：PCT/US0119578

申请日：2001-06-19

Applicant: INFINEON TECHNOLOGIES CORP

Inventor： BEINTNER JOCHEN ,  MICHAELIS ALEXANDER ,  GRUENING ULRIKE ,  SPINDLER OSWALD ,  GABRIC ZVONIMIR

IPC: H01L21/316 ,  H01L21/32 ,  H01L21/8242 ,  H01L21/00

CPC classification number: H01L27/10861 ,  H01L21/31612 ,  H01L21/32 ,  H01L27/1087

Abstract: A method for forming an oxide collar in a trench, in accordance with the present invention, includes forming a trench (104) in a silicon substrate (102), and depositing and recessing a nitride liner (112) in the trench to expose a portion of the silicon substrate on sidewalls of the trench. An oxide (116) is deposited selective to the nitride liner on the portion of the silicon substrate. Residue oxide is removed from surfaces of the nitride liner to form a collar (116) in the trench.

Abstract translation: 根据本发明的在沟槽中形成氧化物环的方法包括在硅衬底（102）中形成沟槽（104），以及沉积和凹入沟槽中的氮化物衬垫（112）以暴露部分 的硅衬底在沟槽的侧壁上。 对硅衬底的部分上的氮化物衬垫选择性地沉积氧化物（116）。 从氮化物衬垫的表面去除残余氧化物，以在沟槽中形成套环（116）。

公开(公告)号：WO0223624A3

公开(公告)日：2002-08-08

申请号：PCT/US0128762

申请日：2001-09-14

Applicant: INFINEON TECHNOLOGIES CORP

Inventor： THWAITE PETER ,  BEINTNER JOCHEN

IPC: H01L21/762 ,  H01L29/10

CPC classification number: H01L29/1033 ,  H01L21/76235

Abstract: An Insulated Gate Field Effect Transistor (IGFET), fabricated using Shallow Trench Isolation (STI), has an edge of a channel region of the IGFET which has a curved shape with a controlled radius of curvature so as to reduce the electric field at the edge of the channel region. A method of controlling the shape of the edge of the channel region is to limit the supply of oxygen to the region at the edge of the channel region during the oxidation process when the side walls of the silicon island, in which the transistor will be formed, are initially covered with a layer of silicon oxide.

Abstract translation: 使用浅沟槽隔离（STI）制造的绝缘栅场效应晶体管（IGFET）具有IGFET的沟道区域的边缘，其具有受控曲率半径的弯曲形状，以便减小边缘处的电场 的通道区域。 控制沟道区域边缘形状的方法是在氧化过程中限制在氧化过程中在沟槽区边缘处的氧气供应，当硅岛的侧壁将形成晶体管时 ，最初被一层氧化硅覆盖。

公开(公告)号：WO0199162A3

公开(公告)日：2002-07-18

申请号：PCT/US0119882

申请日：2001-06-21

Applicant: INFINEON TECHNOLOGIES CORP

Inventor： MICHAELIS ALEXANDER ,  TEWS HELMUT HORST ,  KUDELKA STEPHAN ,  GRUENING ULRIKE ,  BEINTNER JOCHEN ,  SCHROEDER UWE

IPC: H01L21/28 ,  H01L21/336 ,  H01L21/8242 ,  H01L29/04 ,  H01L29/423 ,  H01L29/51 ,  H01L29/78

CPC classification number: H01L21/28211 ,  H01L27/10864 ,  H01L27/10876 ,  H01L29/045 ,  H01L29/42368 ,  H01L29/518 ,  H01L29/66666 ,  H01L29/7827

Abstract: A method of using a selective etch to provide a desired crystal plane orientation on the sidewalls of a deep trench located in a semiconductor substrate, and the device formed therefrom. Preferably, a crystal plane sidewall (212) is used for the channel region, and crystal planes (216) are used in the corner regions of the trench. Gate oxidation may then be performed such that the oxide is thicker in the corner regions (222) than on the oxide (218, 220) on the primary sides of the trench, resulting in self isolation of the corner areas from the transistor channel/active area (224). In addition, the structure is relatively insensitive to active area/deep trench misalignment.

Abstract translation: 一种使用选择性蚀刻以在位于半导体衬底中的深沟槽的侧壁上提供期望的晶面取向的方法和由其形成的器件。 优选地，在沟道区域中使用<100>晶面侧壁（212），并且在沟槽的拐角区域中使用<110>晶面（216）。 然后可以执行栅极氧化，使得在角区域（222）中的氧化物比在沟槽的初级侧上的氧化物（218,220）上更厚，导致拐角区域与晶体管沟道/活性物质的自我隔离 区域（224）。 此外，该结构对有源区/深沟槽未对准相对不敏感。

公开(公告)号：EP1711966A4

公开(公告)日：2011-02-16

申请号：EP04704467

申请日：2004-01-22

Applicant: IBM

Inventor： BEINTNER JOCHEN ,  CHIDAMBARRAO DURESETI ,  DIVKARUNI RAMACHANDRA

IPC: H01L29/786 ,  H01L21/336 ,  H01L21/8238

CPC classification number: H01L29/78642 ,  H01L21/2257 ,  H01L29/66787

公开(公告)号：EP1935020A4

公开(公告)日：2009-08-12

申请号：EP06825028

申请日：2006-09-19

Applicant: IBM

Inventor： BEINTNER JOCHEN ,  LUDWIG THOMAS ,  NOWAK EDWARD J

IPC: H01L21/84 ,  H01L21/336 ,  H01L27/12 ,  H01L29/78

CPC classification number: H01L21/845 ,  H01L27/1211 ,  H01L29/66795 ,  H01L29/785

Abstract: A method, structure and alignment procedure, for forming a finFET. The method including, defining a first fin of the finFET with a first mask and defining a second fin of the finFET with a second mask. The structure including integral first and second fins of single-crystal semiconductor material and longitudinal axes of the first and second fins aligned in the same crystal direction but offset from each other. The alignment procedure including simultaneously aligning alignment marks on a gate mask to alignment targets formed separately by a first masked used to define the first fin and a second mask used to define the second fin.