公开(公告)号：JP2000323684A

公开(公告)日：2000-11-24

申请号：JP2000085406

申请日：2000-03-24

Applicant: INFINEON TECHNOLOGIES CORP ,  IBM

Inventor： GRUENING ULRIKE ,  HALLE SCOTT ,  RADENS CARL J ,  JEFFREY J WERSER ,  BEINTNER JOCHEN ,  MANDELMAN JACK A ,  WITTMANN JUERGEN

IPC: H01L27/108 ,  H01L21/8242

Abstract: PROBLEM TO BE SOLVED: To form a trench capacitor in a semiconductor body. SOLUTION: A trench capacitor 10 and a MOS transistor 9 are provided in a substrate 16 to form a cell 8 of the DRAM, and the cell 8 is separated from adjacent cells by an STI region 28. The capacitor 10 is composed of an insulator 14 enveloping the trench and a first electrode 24 filled with polysilicon 12, is connected to the drain portion 72 through a buried electrode 22, and is insulated from a gate electrode 20 by a dielectric 23. A second electrode 25 is formed in its bottom portion through an insulator 14. A transistor 9 has N-type drain 72 and source 71 in an upper active region 11 of the substrate 16 and operates with a p well as channel.

公开(公告)号：JP2000031086A

公开(公告)日：2000-01-28

申请号：JP17744999

申请日：1999-06-23

Applicant: SIEMENS AG ,  IBM

Inventor： WITTMANN JUERGEN ,  BRUNO SPULER ,  DOBUZINSKY DAVE ,  WOLFGANG BERGNER

IPC: H01L21/311 ,  H01L21/336 ,  H01L21/60 ,  H01L21/768 ,  H01L29/78 ,  H01L21/28 ,  H01L21/31

Abstract: PROBLEM TO BE SOLVED: To reduce the possibility of an electric fail in a semiconductor device by depositing an insulating layer on a gate stack formed in manufacture, etching the insulating layer, and forming a spacer which insulates/separates the gate stack from a contact point area. SOLUTION: The spacer layer of nitride, oxide or oxide/nitride is deposited after a CB (bit line contact point) nitride liner is etched and it is operated as an insulating layer. The spacer layer of insulating nitride, oxide or oxide/ nitride is etched and it is sufficiently insulated from a transistor element. It becomes a contact point with a diffusion area and inhibits the opening of CB. The gate stack forming process of an SAC process is executed on a gate oxide layer in a usual way. SiN or SiON is deposited on a gate stack and BPSG and TEOS are continuously deposited. Then, chemical/mechanical polishing is executed after BPSG is deposited and before TEOS is deposited.

公开(公告)号：JP2000082800A

公开(公告)日：2000-03-21

申请号：JP22931499

申请日：1999-08-13

Applicant: IBM ,  SIEMENS AG

Inventor： BRONNER GARY B ,  KAARU JIEI RADENSU ,  WITTMANN JUERGEN

IPC: H01L27/108 ,  H01L21/8242 ,  H01L27/10

Abstract: PROBLEM TO BE SOLVED: To form a buried strap through a simplified process by a structure wherein the part of second conductive material positioned between the depth of a strap and the upper surface of a trench includes a buried strap. SOLUTION: The method for forming a strap comprises a step for making a trench 200 in a substrate 201, a step for filling the trench 200 partially with a first conductive material 202, and a step for applying a color material 203 to the part of the trench 200 on the first conductive material 202. The method further comprises a step for etching the color material 203 down to the depth of a strap 205 beneath the upper surface of the trench 200, and a step for filling the trench 200 with a second conductive material 210. The part of second conductive material 210 positioned between the depth of the strap 205 and the upper surface of the trench 200 is formed while including the buried strap. 205.

公开(公告)号：DE69807621T2

公开(公告)日：2003-11-27

申请号：DE69807621

申请日：1998-06-26

Applicant: INFINEON TECHNOLOGIES AG ,  IBM

Inventor： LEVY MAX G ,  FIEGL BERNHARD ,  BERGNER WOLFGANG ,  GOTH GEORGE R ,  PARRIES PAUL ,  SENDELBACH MATTHEW J ,  WANG TING-HAO ,  WILLE WILLIAM C ,  WITTMANN JUERGEN

IPC: H01L21/302 ,  H01L21/304 ,  H01L21/306 ,  H01L21/3105 ,  H01L21/76 ,  H01L21/321

Abstract: A method for preventing CMP-induced (chemical-mechanical polish) damage to a substrate disposed below a pad nitride layer of a mesa. The pad nitride layer is disposed below a conformally deposited dielectric layer. The dielectric layer is disposed below a conformally deposited polysilicon layer. The method includes planarizing the polysilicon layer down to at least a surface of the dielectric layer using the CMP to expose a first region of the dielectric layer. The method further includes etching partially through the first region of the dielectric layer using first etch parameters. The first etch parameters include an etchant source gas that is substantially selective to the pad nitride layer to prevent the pad nitride layer from being etched through even in the presence of a CMP defect. Additionally, there is also included removing the polysilicon layer after the etching partially through the first region of the dielectric layer.

公开(公告)号：DE69807621D1

公开(公告)日：2002-10-10

申请号：DE69807621

申请日：1998-06-26

Applicant: SIEMENS AG ,  IBM

Inventor： LEVY MAX G ,  FIEGL BERNHARD ,  BERGNER WOLFGANG ,  GOTH GEORGE R ,  PARRIES PAUL ,  SENDELBACH MATTHEW J ,  WANG TING-HAO ,  WILLE WILLIAM C ,  WITTMANN JUERGEN

IPC: H01L21/302 ,  H01L21/304 ,  H01L21/306 ,  H01L21/3105 ,  H01L21/76 ,  H01L21/321

Abstract: A method for preventing CMP-induced (chemical-mechanical polish) damage to a substrate disposed below a pad nitride layer of a mesa. The pad nitride layer is disposed below a conformally deposited dielectric layer. The dielectric layer is disposed below a conformally deposited polysilicon layer. The method includes planarizing the polysilicon layer down to at least a surface of the dielectric layer using the CMP to expose a first region of the dielectric layer. The method further includes etching partially through the first region of the dielectric layer using first etch parameters. The first etch parameters include an etchant source gas that is substantially selective to the pad nitride layer to prevent the pad nitride layer from being etched through even in the presence of a CMP defect. Additionally, there is also included removing the polysilicon layer after the etching partially through the first region of the dielectric layer.