公开(公告)号：WO0223586A3

公开(公告)日：2002-06-27

申请号：PCT/US0128440

申请日：2001-09-13

Applicant: INFINEON TECHNOLOGIES CORP ,  IBM

Inventor： ATHAVALE SATISH ,  LEE BRIAN ,  LEE HEON ,  LEE KILHO ,  LIMB YOUNG ,  PARK YOUNG JIN ,  SIM JAI-HOON

IPC: H01J37/32

CPC classification number: H01J37/32412 ,  H01J37/32706 ,  H01J2237/334

Abstract: Apparatus for etching a patterned layer of a noble metal such as platinum. The apparatus implements a process whereby exposed areas of the noble metal are first implanted with ions and are subsequently etched. Both the ion implantation step and the etching step occur sequentially in the same chamber in the presence of a plasma discharge. The apparatus uses either a dual output power supply or two distinct power supplies to sequentially supply a high power output required for the ion implantation step and a low power output required for the etching step. Multiple cycles of implantation followed by etching may be applied to achieve deep etching of thick layers. A programmed computer controls the process steps. A method of using the apparatus is also provided.

Abstract translation: 蚀刻贵金属如铂的图案化层的设备。 该设备实施一种方法，由此首先将贵金属的暴露区域注入离子并随后进行蚀刻。 在存在等离子体放电的情况下，离子注入步骤和蚀刻步骤在相同的腔室中顺序地发生。 该装置使用双输出电源或两个不同的电源来顺序地提供离子注入步骤所需的高功率输出和蚀刻步骤所需的低功率输出。 可以应用多次注入之后的蚀刻以实现厚层的深刻蚀。 编程的计算机控制过程步骤。 还提供了使用该设备的方法。

公开(公告)号：WO0203423A3

公开(公告)日：2002-08-08

申请号：PCT/US0121164

申请日：2001-07-02

Applicant: INFINEON TECHNOLOGIES CORP ,  IBM

Inventor： DYER THOMAS W ,  KUNKEL GERHARD ,  HSU LOUIS L ,  LEE HEON ,  KOTECKI DAVID ,  LIMB YOUNG ,  RADENS CARL J ,  PARK YOUNG JIN

IPC: H01L21/8242 ,  H01L23/528 ,  H01L23/532

CPC classification number: H01L27/10852 ,  H01L23/5283 ,  H01L23/53228 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A DRAM cell and method of fabrication are provided that eliminate critical photolithography fabrication steps by merging stacked capacitor formation with electrical contacts. The a single lithography step can be used to form the electrical contacts (28) because the stacked capacitors (46,48,50) are co-planar with the bit lines (36) and the stacked capacitors are located in the insulating material provided between the bit lines. Unlike conventional capacitor-over-bit line (COB) DRAM cells, this capacitor-beside-bit line DRAM cell eliminates the need to dedicate contacts to the capacitor, making it possible to achieve higher capacitance with lower global topography.

Abstract translation: 提供了一种DRAM单元和制造方法，其通过将堆叠的电容器形成与电触点并入来消除关键的光刻制造步骤。 由于层叠的电容器（46,48,50）与位线（36）是共面的，所以单个光刻步骤可用于形成电触点（28），并且堆叠的电容器位于设置在 位线。 与常规的电容器位线（COB）DRAM单元不同，这种位线旁边的DRAM电池消除了将触点专用于电容器的需要，使得可以在较低的全局地形下实现更高的电容。

公开(公告)号：WO0203423A8

公开(公告)日：2002-04-11

申请号：PCT/US0121164

申请日：2001-07-02

Applicant: INFINEON TECHNOLOGIES CORP ,  IBM

Inventor： DYER THOMAS W ,  KUNKEL GERHARD ,  HSU LOUIS L ,  LEE HEON ,  KOTECKI DAVID ,  LIMB YOUNG ,  RADENS CARL J ,  PARK YOUNG JIN

IPC: H01L21/8242 ,  H01L23/528 ,  H01L23/532 ,  H01L

CPC classification number: H01L27/10852 ,  H01L23/5283 ,  H01L23/53228 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A DRAM cell and method of fabrication are provided that eliminate critical photolithography fabrication steps by merging stacked capacitor formation with electrical contacts. The a single lithography step can be used to form the electrical contacts because the stacked capacitors are co-planar with the bit lines and the stacked capacitors are located in the insulating material provided between the bit lines. Unlike conventional capacitor-over-bit line (COB) DRAM cells, this capacitor-beside-bit line DRAM cell eliminates the need to dedicate contacts to the capacitor, making it possible to achieve higher capacitance with lower global topography.

Abstract translation: 提供DRAM单元和制造方法，其通过将堆叠的电容器结构与电触点合并来消除关键的光刻制造步骤。 因为堆叠的电容器与位线共面并且堆叠的电容器位于位线之间提供的绝缘材料中，所以可以使用单个光刻步骤来形成电触点。 与传统的电容器位线（COB）DRAM单元不同，这种位于电容器旁边的位线DRAM单元消除了对电容器专用接触的需要，使得可以用较低的全局地形实现更高的电容。

公开(公告)号：WO0154183A3

公开(公告)日：2002-02-28

申请号：PCT/US0101887

申请日：2001-01-18

Applicant: INFINEON TECHNOLOGIES CORP ,  IBM

Inventor： LEE HEON ,  PARK YOUNG-JIN ,  LIMB YOUNG ,  LEE BRIAN ,  LEE KILHO ,  ATHAVALE SATISH

IPC: H01L21/02 ,  H01L21/314 ,  H01L21/8242 ,  H01L21/316

CPC classification number: H01L28/75 ,  H01L27/10852 ,  H01L28/55

Abstract: In a method of forming a microelectronic structure of a Pt/BSTO/Pt capacitor stack for use in a DRAM device, the improvement comprising substantially eliminating or preventing oxygen out-diffusion from the BSTO material layer, comprising: preparing a bottom Pt electrode formation; subjecting the bottom Pt electrode formation to an oxygen plasma treatment to form an oxygen enriched Pt layer on the bottom Pt electrode; depositing a BSTO layer on said oxygen enriched Pt layer; depositing an upper Pt electrode layer on the BSTO layer; subjecting the upper Pt electrode layer to an oxygen plasma treatment to form an oxygen incorporated Pt layer; and depositing a Pt layer on the oxygen incorporated Pt layer upper Pt elect.

Abstract translation: 在形成用于DRAM器件的Pt / BSTO / Pt电容器堆叠的微电子结构的方法中，改进包括基本上消除或防止来自BSTO材料层的氧扩散，包括：制备底部Pt电极形成; 使底Pt电极形成氧等离子体处理，在底Pt电极上形成富氧Pt层; 在所述富氧Pt层上沉积BSTO层; 在BSTO层上沉积上部Pt电极层; 使上Pt电极层进行氧等离子体处理以形成掺入氧的Pt层; 并在掺有氧的Pt层上部Pt上沉积Pt层。

公开(公告)号：DE102004016963A1

公开(公告)日：2004-11-18

申请号：DE102004016963

申请日：2004-04-06

Applicant: INFINEON TECHNOLOGIES AG ,  IBM

Inventor： WISE MICHAEL ,  LIMB YOUNG ,  WONG KWONG HON ,  LIAN JENNY ,  NAGEL NICOLAS

IPC: B32B9/04 ,  B32B15/04 ,  H01L21/02 ,  H01L21/8239 ,  H01L21/8242

Abstract: Si, Al, Al plus TiN, and IrO2 are used as adhesion layers to prevent peeling of noble metal electrodes, such as Pt, from a silicon dioxide (SiO 2 ) substrate in capacitor structures of memory devices.