公开(公告)号：WO0193323A3

公开(公告)日：2002-06-27

申请号：PCT/US0115997

申请日：2001-05-18

Applicant: INFINEON TECHNOLOGIES CORP ,  IBM

Inventor： NAEEM MUNIR D ,  LEE BRIAN S ,  MATHAD GANGADHARA S ,  LEE HEON ,  KIM BYEONG YEOL ,  MORALES ELIZABETH ,  KUDELKA STEPHAN P ,  RANADE RAJIV ,  PARK YOUNG-JIN

IPC: H01L21/302 ,  H01L21/3065 ,  H01L21/308 ,  H01L21/8242 ,  H01L27/108 ,  H01L21/311 ,  H01L21/8239

CPC classification number: H01L21/3081 ,  H01L21/3065

Abstract: A method of minimizing RIE lag (i.e., the neutral and ion fluxes at the bottom of a deep trench (DT) created during the construction of the trench opening using a side wall film deposition)) in DRAMs having a large aspect ratio (i.e., > 30:1) is described. The method forms a passivation film to the extent necessary for preventing isotropic etching of the substrate, hence maintaining the required profile and the shape of the DT within the substrate. The RIE process described provides a partial DT etched into a substrate to achieve the predetermined depth. The passivation film is allowed to grow to a certain thickness still below the extent that it would close the opening of the deep trench. Alternatively, the passivation film is removed by a non-RIE etching process. The non-RIE process that removes the film can be wet etched with chemicals, such as hydrofluoric acid (buffered or non buffered) or, alternatively, using vapor phase and/or non-ionized chemicals, such as anhydrous hydrofluoric acid. The controlled thickness of the film allows achieving a predetermined DT depth for high aspect ratio structures

Abstract translation: 最小化RIE滞后的方法（即，在使用侧壁膜沉积的沟槽开口的构造期间产生的深沟槽（DT）的底部处的中性和离子通量））具有大纵横比的DRAM（即， > 30：1）。 该方法形成钝化膜，以防止基板的各向同性蚀刻所必需的程度，从而将所需的轮廓和DT的形状保持在基板内。 所述的RIE工艺提供了蚀刻到衬底中以实现预定深度的部分DT。 允许钝化膜生长到一定厚度，仍然低于其将关闭深沟槽的开口的程度。 或者，通过非RIE蚀刻工艺去除钝化膜。 可以用诸如氢氟酸（缓冲或非缓冲）的化学品或者使用蒸气相和/或非电离化学物质如无水氢氟酸来湿法蚀刻除去膜的非RIE工艺。 膜的受控厚度允许实现高纵横比结构的预定DT深度

公开(公告)号：WO0203423A3

公开(公告)日：2002-08-08

申请号：PCT/US0121164

申请日：2001-07-02

Applicant: INFINEON TECHNOLOGIES CORP ,  IBM

Inventor： DYER THOMAS W ,  KUNKEL GERHARD ,  HSU LOUIS L ,  LEE HEON ,  KOTECKI DAVID ,  LIMB YOUNG ,  RADENS CARL J ,  PARK YOUNG JIN

IPC: H01L21/8242 ,  H01L23/528 ,  H01L23/532

CPC classification number: H01L27/10852 ,  H01L23/5283 ,  H01L23/53228 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A DRAM cell and method of fabrication are provided that eliminate critical photolithography fabrication steps by merging stacked capacitor formation with electrical contacts. The a single lithography step can be used to form the electrical contacts (28) because the stacked capacitors (46,48,50) are co-planar with the bit lines (36) and the stacked capacitors are located in the insulating material provided between the bit lines. Unlike conventional capacitor-over-bit line (COB) DRAM cells, this capacitor-beside-bit line DRAM cell eliminates the need to dedicate contacts to the capacitor, making it possible to achieve higher capacitance with lower global topography.

Abstract translation: 提供了一种DRAM单元和制造方法，其通过将堆叠的电容器形成与电触点并入来消除关键的光刻制造步骤。 由于层叠的电容器（46,48,50）与位线（36）是共面的，所以单个光刻步骤可用于形成电触点（28），并且堆叠的电容器位于设置在 位线。 与常规的电容器位线（COB）DRAM单元不同，这种位线旁边的DRAM电池消除了将触点专用于电容器的需要，使得可以在较低的全局地形下实现更高的电容。

公开(公告)号：WO0223586A3

公开(公告)日：2002-06-27

申请号：PCT/US0128440

申请日：2001-09-13

Applicant: INFINEON TECHNOLOGIES CORP ,  IBM

Inventor： ATHAVALE SATISH ,  LEE BRIAN ,  LEE HEON ,  LEE KILHO ,  LIMB YOUNG ,  PARK YOUNG JIN ,  SIM JAI-HOON

IPC: H01J37/32

CPC classification number: H01J37/32412 ,  H01J37/32706 ,  H01J2237/334

Abstract: Apparatus for etching a patterned layer of a noble metal such as platinum. The apparatus implements a process whereby exposed areas of the noble metal are first implanted with ions and are subsequently etched. Both the ion implantation step and the etching step occur sequentially in the same chamber in the presence of a plasma discharge. The apparatus uses either a dual output power supply or two distinct power supplies to sequentially supply a high power output required for the ion implantation step and a low power output required for the etching step. Multiple cycles of implantation followed by etching may be applied to achieve deep etching of thick layers. A programmed computer controls the process steps. A method of using the apparatus is also provided.

Abstract translation: 蚀刻贵金属如铂的图案化层的设备。 该设备实施一种方法，由此首先将贵金属的暴露区域注入离子并随后进行蚀刻。 在存在等离子体放电的情况下，离子注入步骤和蚀刻步骤在相同的腔室中顺序地发生。 该装置使用双输出电源或两个不同的电源来顺序地提供离子注入步骤所需的高功率输出和蚀刻步骤所需的低功率输出。 可以应用多次注入之后的蚀刻以实现厚层的深刻蚀。 编程的计算机控制过程步骤。 还提供了使用该设备的方法。

公开(公告)号：WO0203423A8

公开(公告)日：2002-04-11

申请号：PCT/US0121164

申请日：2001-07-02

Applicant: INFINEON TECHNOLOGIES CORP ,  IBM

Inventor： DYER THOMAS W ,  KUNKEL GERHARD ,  HSU LOUIS L ,  LEE HEON ,  KOTECKI DAVID ,  LIMB YOUNG ,  RADENS CARL J ,  PARK YOUNG JIN

IPC: H01L21/8242 ,  H01L23/528 ,  H01L23/532 ,  H01L

CPC classification number: H01L27/10852 ,  H01L23/5283 ,  H01L23/53228 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A DRAM cell and method of fabrication are provided that eliminate critical photolithography fabrication steps by merging stacked capacitor formation with electrical contacts. The a single lithography step can be used to form the electrical contacts because the stacked capacitors are co-planar with the bit lines and the stacked capacitors are located in the insulating material provided between the bit lines. Unlike conventional capacitor-over-bit line (COB) DRAM cells, this capacitor-beside-bit line DRAM cell eliminates the need to dedicate contacts to the capacitor, making it possible to achieve higher capacitance with lower global topography.

Abstract translation: 提供DRAM单元和制造方法，其通过将堆叠的电容器结构与电触点合并来消除关键的光刻制造步骤。 因为堆叠的电容器与位线共面并且堆叠的电容器位于位线之间提供的绝缘材料中，所以可以使用单个光刻步骤来形成电触点。 与传统的电容器位线（COB）DRAM单元不同，这种位于电容器旁边的位线DRAM单元消除了对电容器专用接触的需要，使得可以用较低的全局地形实现更高的电容。

公开(公告)号：WO0154183A3

公开(公告)日：2002-02-28

申请号：PCT/US0101887

申请日：2001-01-18

Applicant: INFINEON TECHNOLOGIES CORP ,  IBM

Inventor： LEE HEON ,  PARK YOUNG-JIN ,  LIMB YOUNG ,  LEE BRIAN ,  LEE KILHO ,  ATHAVALE SATISH

IPC: H01L21/02 ,  H01L21/314 ,  H01L21/8242 ,  H01L21/316

CPC classification number: H01L28/75 ,  H01L27/10852 ,  H01L28/55

Abstract: In a method of forming a microelectronic structure of a Pt/BSTO/Pt capacitor stack for use in a DRAM device, the improvement comprising substantially eliminating or preventing oxygen out-diffusion from the BSTO material layer, comprising: preparing a bottom Pt electrode formation; subjecting the bottom Pt electrode formation to an oxygen plasma treatment to form an oxygen enriched Pt layer on the bottom Pt electrode; depositing a BSTO layer on said oxygen enriched Pt layer; depositing an upper Pt electrode layer on the BSTO layer; subjecting the upper Pt electrode layer to an oxygen plasma treatment to form an oxygen incorporated Pt layer; and depositing a Pt layer on the oxygen incorporated Pt layer upper Pt elect.

Abstract translation: 在形成用于DRAM器件的Pt / BSTO / Pt电容器堆叠的微电子结构的方法中，改进包括基本上消除或防止来自BSTO材料层的氧扩散，包括：制备底部Pt电极形成; 使底Pt电极形成氧等离子体处理，在底Pt电极上形成富氧Pt层; 在所述富氧Pt层上沉积BSTO层; 在BSTO层上沉积上部Pt电极层; 使上Pt电极层进行氧等离子体处理以形成掺入氧的Pt层; 并在掺有氧的Pt层上部Pt上沉积Pt层。

公开(公告)号：DE10219841A1

公开(公告)日：2003-02-13

申请号：DE10219841

申请日：2002-05-03

Applicant: INFINEON TECHNOLOGIES CORP ,  IBM

Inventor： PARK YOUNGJIN ,  COSTRINI GREG ,  KOTECKI DAVID E ,  LEE HEON

IPC: H01L21/60 ,  H01L21/768 ,  H01L21/8242 ,  H01L27/108 ,  H01L21/283

Abstract: Methods for fabricating a semiconductor device are disclosed. Parallel gate structures are formed on a substrate with spaces between the gate structures. A blanket depositing of a conductive material is performed to fill the spaces and cover the gate structures such that contact with the substrate is made by the conductive material. A mask is patterned to remain over active area regions. The mask remains over the spaces. The conductive material is removed in accordance with the mask to provide contacts formed from the conductive material which fills the spaces over the active areas. A dielectric layer is deposited over the gate structures and over the contacts. Holes down to the contacts are formed, and a conductive region is connected to the contacts through the holes.

公开(公告)号：DE10219841B4

公开(公告)日：2007-11-29

申请号：DE10219841

申请日：2002-05-03

Applicant: INFINEON TECHNOLOGIES CORP ,  IBM

Inventor： PARK YOUNGJIN ,  COSTRINI GREG ,  KOTECKI DAVID E ,  LEE HEON

IPC: H01L21/283 ,  H01L21/60 ,  H01L21/768 ,  H01L21/8242 ,  H01L27/108

Abstract: Methods for fabricating a semiconductor device are disclosed. Parallel gate structures are formed on a substrate with spaces between the gate structures. A blanket depositing of a conductive material is performed to fill the spaces and cover the gate structures such that contact with the substrate is made by the conductive material. A mask is patterned to remain over active area regions. The mask remains over the spaces. The conductive material is removed in accordance with the mask to provide contacts formed from the conductive material which fills the spaces over the active areas. A dielectric layer is deposited over the gate structures and over the contacts. Holes down to the contacts are formed, and a conductive region is connected to the contacts through the holes.

公开(公告)号：WO0145175A2

公开(公告)日：2001-06-21

申请号：PCT/US0034035

申请日：2000-12-13

Applicant: INFINEON TECHNOLOGIES CORP

Inventor： LEE HEON ,  PARK YOUNG-JIN

IPC: H01L21/266 ,  H01L21/28 ,  H01L21/3213 ,  H01L21/336 ,  H01L29/00

CPC classification number: H01L29/66598 ,  H01L21/266 ,  H01L21/28035 ,  H01L21/28123 ,  H01L21/32137

Abstract: A method for forming a transistor is formed where a gate electrode of the transistor is formed over a substrate defining a gate channel portion of the substrate. A mask is also formed over the substrate, a portion of the mask extending over a first portion of the substrate adjacent to the gate channel portion of the substrate. The mask defines a second portion of the substrate adjacent to the first portion of the substrate. An ion beam is directed toward the substrate to form a drain or a source region of said transistor adjacent to the gate channel portion of the substrate, the source or drain region including the first and second portions of the substrate. The ion beam implants the second portion of the substrate with a first implantation characteristic. The ion beam passes through the extended portion of the mask to reach the first portion to implant the first portion with a second implantation characteristic, such second implantation characteristic being different from the first implantation characteristic.

Abstract translation: 形成晶体管的方法形成在晶体管的栅电极形成在限定衬底的栅极沟道部分的衬底上。 掩模也形成在衬底上，掩模的一部分在与衬底的栅极沟道部分相邻的衬底的第一部分上延伸。 掩模限定与基板的第一部分相邻的基板的第二部分。 离子束指向衬底以形成与衬底的栅极沟道部分相邻的所述晶体管的漏极或源极区域，源极或漏极区域包括衬底的第一和第二部分。 离子束以第一注入特性注入衬底的第二部分。 离子束通过掩模的延伸部分到达第一部分，以第二注入特性注入第一部分，这种第二注入特性与第一注入特性不同。

公开(公告)号：WO0225728A2

公开(公告)日：2002-03-28

申请号：PCT/US0126648

申请日：2001-08-27

Applicant: INFINEON TECHNOLOGIES CORP

Inventor： LEE HEON

IPC: H01L21/3105 ,  H01L21/311 ,  H01L21/316 ,  H01L21/8234

CPC classification number: H01L21/31111 ,  H01L21/3105 ,  H01L21/31662 ,  H01L21/823462

Abstract: A method of forming on a common semiconductor body (substrate) silicon oxide layers of different thicknesses uses plasma treatment on selected portions of an original thermally grown silicon oxide layer. The plasma treated portions are completely etched away to expose a portion of the surface of the body while non-selected portions of the original silicon oxide layer are little effected by the etch. A thermally grown second layer of silicon oxide is formed with the result being that the silicon oxide layer formed in the exposed portions of the body is thinner than elsewhere. The use of dual thickness silicon oxide layers is useful with dynamic random access memories (DRAMs) as gate oxide layers of field transistors of memory cells of the DRAM typically require different electrical characteristics than transistors of support circuitry of the DRAM

Abstract translation: 在公共半导体基体（基体）上形成不同厚度的氧化硅层的方法在原始热生长硅氧化物层的选定部分上使用等离子体处理。 等离子体处理部分被完全蚀刻掉以暴露主体表面的一部分，而原始氧化硅层的非选择部分几乎不受蚀刻的影响。 形成热生长的第二氧化硅层，其结果是形成在主体的暴露部分中的氧化硅层比别处更薄。 由于DRAM的存储器单元的场效应晶体管的栅极氧化层通常需要与DRAM的支持电路的晶体管不同的电特性，所以使用双厚度氧化硅层对于动态随机存取存储器（DRAM）是有用的

公开(公告)号：WO0199174A2

公开(公告)日：2001-12-27

申请号：PCT/US0119583

申请日：2001-06-19

Applicant: INFINEON TECHNOLOGIES CORP

Inventor： LEE HEON ,  PARK YOUNG-JIN

IPC: H01L21/28 ,  H01L21/316 ,  H01L21/3213 ,  H01L21/8234 ,  H01L21/334

CPC classification number: H01L21/32137 ,  H01L21/28123 ,  H01L21/31629 ,  H01L21/823481

Abstract: In a process for etching poly Si gate stacks with raised STI structure where the thickness of poly Si gates at the AA and STI are different, the improvement comprising: (a) etching a gate silicide layer + a poly Si 2 layer; (b) forming a continuous poly Si passivation layer on sidewalls of the silicide and poly Si 2 layers and at the interface of the poly Si 2 layer and a poly Si 1 layer and affecting thermal oxidation to form an underlying thin Si oxide gate layer; (c) affecting a Si oxide breakthrough etch to clear the passivation layer at interface of the poly Si 2 and the poly Si 1 layers while leaving intact the passivation layer on the sidewalls of the silicide and the poly Si 2 layers; and (d) etching the poly Si 1 layer with an oxide selective process to preserve the underlying thin gate oxide and thin passivation layer at the sidewall to obtain vertical profiles of poly Si gate stacks both at the AA and the STI oxide.

Abstract translation: 在用于蚀刻具有凸起STI结构的多晶硅栅极堆叠的过程中，其中在AA和STI处的多晶硅栅极的厚度不同，改进包括：（a）蚀刻栅极硅化物层+多晶硅层; （b）在硅化物和多晶硅层的侧壁上以及在多晶硅层和多晶硅层的界面处形成连续的多晶硅钝化层，并影响热氧化以形成下薄的氧化硅栅极层; （c）影响Si氧化物穿透蚀刻以在多晶Si 2和多晶硅层1的界面处清除钝化层，同时将钝化层完整地保留在硅化物和多晶硅层的侧壁上; 和（d）用氧化物选择性工艺蚀刻多晶硅层1以在侧壁处保留下面的薄栅极氧化物和薄的钝化层，以在AA和STI氧化物上获得多晶硅栅叠层的垂直分布。