公开(公告)号：US20240334838A1

公开(公告)日：2024-10-03

申请号：US18293846

申请日：2022-03-02

Applicant: INSTITUTE OF MICROELECTRONICS, CHINESE ACADEMY OF SCIENCES

Inventor： Guozhong Xing ,  Long Liu ,  Xuefeng Zhao ,  Di Wang ,  Huai Lin ,  Hao Zhang ,  Ziwei Wang

IPC: H10N50/10 ,  G11C5/06 ,  G11C11/16 ,  H10B61/00 ,  H10N50/20 ,  H10N50/85 ,  H10N52/00

CPC classification number: H10N50/10 ,  G11C5/063 ,  G11C11/161 ,  G11C11/1673 ,  G11C11/1675 ,  H10B61/20 ,  H10N50/20 ,  H10N50/85 ,  H10N52/101

Abstract: The present disclosure provides an SOT-MRAM memory cell, including: a bottom electrode; a magnetic tunnel junction layer located on the bottom electrode; an orbital Hall effect layer located on the magnetic tunnel junction layer; a first transistor, a drain of which is connected to the orbital Hall effect layer; and a second transistor, a drain of which is connected to the bottom electrode. The present disclosure further provides an SOT-MRAM memory, an operation method, and an SOT-MRAM memory array.

公开(公告)号：US20230263070A1

公开(公告)日：2023-08-17

申请号：US18003913

申请日：2020-12-31

Applicant: INSTITUTE OF MICROELECTRONICS, CHINESE ACADEMY OF SCIENCES

Inventor： Guozhong Xing ,  Di Wang ,  Huai Lin ,  Long Liu ,  Yu Liu ,  Hangbing Lv ,  Changqing Xie ,  Ling Li ,  Ming Liu

IPC: H10N50/10 ,  H10B61/00 ,  H10N50/85 ,  G11C11/16

CPC classification number: H10N50/10 ,  H10B61/22 ,  H10N50/85 ,  G11C11/161

Abstract: The present disclosure relates to a field of memory technical, and in particular to a magnetoresistive device, a method for changing a resistance state of the magnetoresistive device, and a synapse learning module. The magnetoresistive device includes a top electrode, a ferromagnetic reference layer, a tunneling layer, a ferromagnetic free layer, a spin-orbit coupling layer, and a bottom electrode that are arranged in sequence along a preset direction, where the spin-orbit coupling layer includes a first thickness region and a second thickness region distributed alternately, and a thickness of the first thickness region is different form a thickness of the second thickness region; and the ferromagnetic free layer includes a pinning region, and a position of the pinning region is in one-to-one correspondence with a position of the first thickness region.

公开(公告)号：US20240013826A1

公开(公告)日：2024-01-11

申请号：US18251699

申请日：2021-10-13

Applicant: INSTITUTE OF MICROELECTRONICS, CHINESE ACADEMY OF SCIENCES

Inventor： Guozhong Xing ,  Di Wang ,  Long Liu ,  Huai Lin ,  Ming Liu

IPC: G11C11/16 ,  H10B61/00 ,  H10N50/20 ,  G06F17/16

CPC classification number: G11C11/161 ,  H10B61/22 ,  H10N50/20 ,  G11C11/1655 ,  G11C11/1657 ,  G11C11/1675 ,  G06F17/16

Abstract: Provided is a spintronic device, a memory cell, a memory array, and a read and write circuit applied in a field of integration technology. The spintronic device includes: a bottom electrode; a spin orbit coupling layer, arranged on the bottom electrode; at least one pair of magnetic tunnel junctions, arranged on the spin orbit coupling layer, wherein each of the magnetic tunnel junctions includes a free layer, a tunneling layer, and a reference layer arranged sequentially from bottom to top, and wherein magnetization directions of reference layers of two magnetic tunnel junctions of each pair of the magnetic tunnel junctions are opposite; and a top electrode, arranged on a reference layer of each of the magnetic tunnel junctions.

公开(公告)号：US12293781B2

公开(公告)日：2025-05-06

申请号：US18261716

申请日：2021-01-21

Applicant: INSTITUTE OF MICROELECTRONICS, CHINESE ACADEMY OF SCIENCES

Inventor： Huai Lin ,  Guozhong Xing ,  Zuheng Wu ,  Long Liu ,  Di Wang ,  Cheng Lu ,  Peiwen Zhang ,  Changqing Xie ,  Ling Li ,  Ming Liu

IPC: G11C11/16

Abstract: The three-state spintronic device includes: a bottom electrode, a magnetic tunnel junction and a top electrode from bottom to top. The magnetic tunnel junction includes: a spin-orbit coupling layer, a ferromagnetic free layer, a barrier tunneling layer, a ferromagnetic reference layer, three local magnetic domain wall pinning centers and domain wall nucleation centers. An antisymmetric exchange interaction is modulated, and the magnetic domain wall pinning centers are embedded in an interface between a heavy metal and the ferromagnetic free layer. The magnetic domain wall nucleation centers are at two ends of the ferromagnetic free layer. A current pulse flows through the spin-orbit coupling layer to generate a spin current and the spin current is injected into the ferromagnetic free layer. Under a control of all-electrical controlled, an effective field of a spin-orbit torque drives domain wall to move and displace.

公开(公告)号：US20230276637A1

公开(公告)日：2023-08-31

申请号：US18003038

申请日：2020-06-24

Applicant: Institute of Microelectronics, Chinese Academy of Sciences

Inventor： Guozhong Xing ,  Huai Lin ,  Ming Liu

IPC: H10B61/00 ,  H10N52/85

CPC classification number: H10B61/10 ,  H10N52/85

Abstract: Provided are a spin orbit torque magnetic random access memory cell, a memory array and a memory, wherein the spin orbit torque magnetic random access memory cell includes: a magnetic tunnel and a selector; the selector is a two-dimensional material based selector; the magnetic tunnel junction is arranged above or below the selector; the magnetic tunnel junction includes an antiferromagnetic layer and a free layer; the free layer is adjacent to the antiferromagnetic layer; when the selector is turned on, the memory cell is conducted, a current generates a spin current which is injected into the free layer, and a magnetization direction of the free layer is switched by the exchange bias effect between the free layer and the antiferromagnetic layer. A deterministic magnetization switching of SOT-MRAM memory cell under zero magnetic field at room temperature may be implemented without an external magnetic field by using the exchange bias effect and applying an optimized bias voltage of the magnetic tunnel junction, so as to achieve a purpose of data writing and implement SOT-MRAM memory cell with double terminal structure.