公开(公告)号：US20240421032A1

公开(公告)日：2024-12-19

申请号：US18703924

申请日：2021-11-02

Applicant: INSTITUTE OF MICROELECTRONICS, CHINESE ACADEMY OF SCIENCES

Inventor： Gang ZHANG ,  Chunlong LI ,  Zongliang HUO ,  Tianchun YE

IPC: H01L23/373 ,  G11C16/14 ,  G11C16/26 ,  H01L23/34 ,  H10B41/27 ,  H10B41/35 ,  H10B43/27 ,  H10B43/35

Abstract: The memory cell includes: an array of channel layers including N channel layers vertically provided on a substrate, a tunneling layer and a memory layer being sequentially provided on an outer side of the channel layers; N thermal conductive cores provided in the N channel layers respectively and penetrating the substrate; and an array of thermocouples including a thermocouple word line layer grown on the substrate and N thermocouple layers on the thermocouple word line layer, the thermocouple layers being connected one-to-one with the thermal conductive cores. A first potential difference is applied between the thermocouple word line layer and the thermocouple layer, and the thermal conductive core connected with the thermocouple layer is heated, so that the channel layer and the memory layer corresponding to the thermal conductive core are maintained at first and second preset temperatures respectively under a thermal insulation effect of the tunneling layer.

公开(公告)号：US20150303274A1

公开(公告)日：2015-10-22

申请号：US14647360

申请日：2012-12-17

Applicant: INSTITUTE OF MICROELECTRONICS, CHINESE ACADEMY OF SCIENCES

Inventor： Huilong ZHU ,  Jun LUO ,  Chunlong LI

IPC: H01L29/66 ,  H01L21/306 ,  H01L29/16 ,  H01L21/265 ,  H01L29/10 ,  H01L21/321 ,  H01L29/78 ,  H01L21/3105

CPC classification number: H01L29/6681 ,  H01L21/265 ,  H01L21/30604 ,  H01L21/3086 ,  H01L21/31053 ,  H01L21/32115 ,  H01L29/1083 ,  H01L29/16 ,  H01L29/165 ,  H01L29/6656 ,  H01L29/66795 ,  H01L29/66803 ,  H01L29/7848 ,  H01L29/7851

Abstract: A method for manufacturing a fin structure is provided. A method according to an embodiment may include: forming a patterned pattern transfer layer on a substrate; forming a first spacer on sidewalls of the pattern transfer layer; forming a second spacer on sidewalls of the first spacer; selectively removing the pattern transfer layer and the first spacer; and patterning the substrate with the second spacer as a mask, so as to form an initial fin.

Abstract translation: 提供一种制造翅片结构的方法。 根据实施例的方法可以包括：在衬底上形成图案化图案转移层; 在所述图案转移层的侧壁上形成第一间隔物; 在所述第一间隔件的侧壁上形成第二间隔件; 选择性地去除图案转印层和第一间隔物; 并用第二间隔物作为掩模图案化衬底，以形成初始鳍。

公开(公告)号：US20150325452A1

公开(公告)日：2015-11-12

申请号：US14647393

申请日：2012-12-20

Applicant: INSTITUTE OF MICROELECTRONICS, CHINESE ACADEMY OF SCIENCES

Inventor： Huilong ZHU ,  Jun LUO ,  Chunlong LI ,  Jian DENG ,  Chao ZHAO

IPC: H01L21/3105 ,  H01L21/265 ,  H01L21/321 ,  H01L29/66 ,  H01L21/308 ,  H01L21/311 ,  H01L29/10

CPC classification number: H01L21/76229 ,  H01L21/26513 ,  H01L21/308 ,  H01L21/31053 ,  H01L21/31056 ,  H01L21/31105 ,  H01L21/32115 ,  H01L21/32132 ,  H01L21/823481 ,  H01L29/1083 ,  H01L29/66795 ,  H01L29/6681

Abstract: A planarization process, the process including performing first sputtering on a material layer, with an area of the material layer which has a relatively low loading condition for sputtering shielded by a first shielding layer, removing the first shielding layer, and performing second sputtering on the material layer to planarize the material layer.

Abstract translation: 平面化处理，该方法包括在材料层上进行第一溅射，其中材料层的面积具有相对低的负载条件，用于由第一屏蔽层屏蔽的溅射，去除第一屏蔽层，以及在第二溅射 材料层以平坦化材料层。