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公开(公告)号：US20200066984A1
公开(公告)日：2020-02-27
申请号：US16489266
申请日：2017-02-28
Inventor： Qi LIU , Xiaolong ZHAO , Sen LIU , Ming LIU , Hangbing LV , Shibing LONG , Yan WANG , Facai WU
IPC: H01L45/00
Abstract: The present disclosure provides a conductive bridge semiconductor device and a method of manufacturing the same. The conductive bridge semiconductor device includes a lower electrode, a resistive switching functional layer, an ion barrier layer and an active upper electrode from bottom to top, wherein the ion barrier layer is provided with certain holes through which active conductive ions pass. Based on this structure, the precise designing of the holes on the barrier layer facilitates the modulation of the quantity, size and density of the conduction paths in the conductive bridge semiconductor device, which enables that the conductive bridge semiconductor device can be modulated to be a nonvolatile conductive bridge resistive random access memory or a volatile conductive bridge selector. Based on the above method, ultra-low power nonvolatile conductive bridge memory and high driving-current volatile conductive bridge selector with controllable polarity are completed.
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2.发明申请公开(公告)号：US20190115529A1
公开(公告)日：2019-04-18
申请号：US16085400
申请日：2016-03-18
Inventor： Ming LIU , Qing LUO , Xiaoxin XU , Hangbing LV , Shibing LONG , Qi LIU
Abstract: A selector for a bipolar resistive random access memory and a method for fabricating the selector are provided. The method includes: providing a substrate; forming a lower electrode on the substrate, where the lower electrode is made of a metal, and the metal is made up of metal atoms which diffuse under an annealing condition of below 400° C.; forming a first metal oxide layer on the lower electrode; performing an annealing process on the first metal oxide layer to make the metal atoms in the lower electrode diffuse into the first metal oxide layer to form a first metal oxide layer doped with metal atoms; forming a second metal oxide layer on the first metal oxide layer doped with metal atoms; forming an upper electrode layer on the second metal oxide layer; and patterning the upper electrode layer to form an upper electrode.
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Patent Agency Ranking
公开(公告)号：US20210175420A1
公开(公告)日：2021-06-10
申请号：US16616785
申请日：2017-05-26
Inventor： Hangbing LV , Ming LIU , Shibing LONG , Qi LIU
Abstract: A RRAM and a method for fabricating the same, wherein the RRAM comprises: a bottom electrode; an oxide layer containing a bottom electrode metal, disposed on the bottom electrode; a resistance-switching layer, disposed on the oxide layer containing a bottom electrode metal, wherein the resistance-switching layer material is a nitrogen-containing tantalum oxide; an inserting layer, disposed on the resistance-switching layer, wherein the inserting layer material comprises a metal or a semiconductor; a top electrode, disposed on the inserting layer. By providing the to resistance-switching layer with a nitrogen-containing tantalum oxide, compared with Ta2O5, the RRAM of the present disclosure has a low activation voltage and a high on-off ratio, and can enhance the control capability over the device resistance by the number of oxygen vacancies.
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4.发明申请公开(公告)号：US20200335165A1
公开(公告)日：2020-10-22
申请号：US16959225
申请日：2018-01-22
Inventor： Qi LIU , Wei WANG , Sen LIU , Feng ZHANG , Hangbing LV , Shibing LONG , Ming LIU
Abstract: An operation method for integrating logic calculations and data storage based on a crossbar array structure of resistive switching devices. The calculation and storage functions of the method are based on the same hardware architecture, and the data storage is completed while performing calculation, thereby realizing the fusion of calculation and storage. The method includes applying a pulse sequence to a specified word line or bit line by a controller, configuring basic units of resistive switching devices to form different serial-parallel structures, such that three basic logic operations, i.e. NAND, OR, and COPY, are implemented and mutually combined on this basis, thereby implementing 16 types of binary Boolean logic and full addition operations, and on this basis, a method for implementing a parallel logic and full addition operations is provided.
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5.发明申请公开(公告)号：US20190006584A1
公开(公告)日：2019-01-03
申请号：US16064120
申请日：2016-08-12
Inventor： Nianduan LU , Pengxiao SUN , Ling LI , Ming IIU , Qi LIU , Hangbing LV , Shibing LONG
IPC: H01L45/00
Abstract: A method for improving endurance of 3D integrated resistive switching memory, comprising: Step 1: Calculating the temperature distribution in the integrated array by the 3D Fourier heat conduction equation; Step 2, selecting heat transfer mode; Step 3: selecting an appropriate array structure; Step 4: analyzing the influence of integration degree on temperature in the array; Step 5: evaluating the endurance performance in the array; and Step 6: changing the array parameters according to the evaluation result to improve the endurance performance. According to the method of the present invention, based on the thermal transmission mode in the 3D integrated resistive switching device, a suitable 3D integrated array is selected to analyze the influence of the integration degree on the device temperature so as to evaluate and improve the endurance of the 3D integrated resistive switching device.
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公开(公告)号：US20170352806A1
公开(公告)日：2017-12-07
申请号：US15539608
申请日：2014-12-26
Inventor： Hangbing LV , Ming LIU , Qi LIU , Shibing LONG
CPC classification number: H01L45/1206 , H01L27/2481 , H01L45/00 , H01L45/124 , H01L45/141 , H01L45/147 , H01L45/1608 , H01L45/1675 , H01L45/1683
Abstract: There is provided a three-terminal atomic switching device and a method of manufacturing the same, which belongs to the field of microelectronics manufacturing and memory technology. The three-terminal atomic switching device includes: a stack structure including a source terminal and a drain terminal; a vertical trench formed by etching the stack structure; an M8XY6 channel layer formed on an inner wall and a bottom of the vertical trench; and a control terminal formed on a surface of the M8XY6 channel layer, wherein the control terminal fills the vertical trench. The source terminal resistance and the drain terminal resistance are controlled by the control terminal. The invention is based on the three-terminal atomic switching device, and realizes high switching ratio characteristic, simple structure, easy integration, high density and low cost due to high non-linearity of the source-drain resistance with respect to the control terminal voltage, and thus can be used in a gated device in a cross-array structure to inhibit a crosstalk phenomenon caused by the leakage current. The three-terminal atomic switching device proposed by the invention is suitable for a planar stacked cross-array structure and a vertical cross-array structure, so as to realize high-density three-dimensional storage.
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公开(公告)号：US20200058704A1
公开(公告)日：2020-02-20
申请号：US16486614
申请日：2017-02-22
Inventor： Hangbing LV , Qing LUO , Xiaoxin XU , Shibing LONG , Qi LIU , Ming LIU
Abstract: A transition metal oxide based selector, a method for preparing the same and resistive random access memory are provided. The method comprises: S1, forming a tungsten plug on a transistor; S2, using the tungsten plug to function as a lower electrode, and preparing a transition metal layer on the tungsten plug; S3, oxidizing the transition metal layer to convert the transition metal layer into a transition metal oxide layer; and S4, depositing an upper electrode on the transition metal oxide, patterning the upper electrode and the transition metal oxide. The selector of the present disclosure may provide a high current density and has a good uniformity. The formed 1S1R structure may effectively eliminate crosstalk phenomenon in a resistive random access memory array, and effectively increase the storage density without increasing the storage unit area, thereby increasing device integration. In addition, the selector for the resistive random access memory of the present invention has advantages of a simple structure, easy for integration, a low cost, a good uniformity, and compatibility with a CMOS process.
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