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公开(公告)号：US20230267990A1
公开(公告)日：2023-08-24
申请号：US18005101
申请日：2020-08-24
Inventor： Qing LUO , Bing CHEN , Hangbing LV , Ming LIU , Cheng LU
IPC: G11C11/4096 , G11C11/408 , G11C11/4094 , H03K19/017
CPC classification number: G11C11/4096 , G11C11/4085 , G11C11/4094 , H03K19/01742
Abstract: Provided are a symmetric memory cell and a BNN circuit. The symmetric memory cell includes a first complementary structure and a second complementary structure, the second complementary structure being symmetrically connected to the first complementary structure in a first direction, wherein the first complementary structure includes a first control transistor configured to be connected to the second complementary structure, the second complementary structure includes a second control transistor, a drain electrode of the second control transistor and a drain electrode of the first control transistor being symmetrically arranged in the first direction and connected to a bit line, and the symmetric memory cell is configured to store a weight value 1 or 0.
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公开(公告)号：US20210013404A1
公开(公告)日：2021-01-14
申请号：US16767091
申请日：2018-03-28
Inventor： Qing LUO , Hangbing LV , Ming LIU
IPC: H01L45/00
Abstract: The present disclosure provides a self-rectifying resistive memory, including: a lower electrode; a resistive material layer formed on the lower electrode and used as a storage medium; a barrier layer formed on the resistive material layer and using a semiconductor material or an insulating material; and an upper electrode formed on the barrier layer to achieve Schottky contact with the material of the barrier layer; wherein, the Schottky contact between the upper electrode and the material of the barrier layer is used to realize self-rectification of the self-rectifying resistive memory. Thus, no additional gate transistor or diode is required as the gate unit. In addition, because the device has self-rectifying characteristics, it is capable of suppressing read crosstalk in the cross-array.
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3.发明申请公开(公告)号：US20190115529A1
公开(公告)日：2019-04-18
申请号：US16085400
申请日：2016-03-18
Inventor： Ming LIU , Qing LUO , Xiaoxin XU , Hangbing LV , Shibing LONG , Qi LIU
Abstract: A selector for a bipolar resistive random access memory and a method for fabricating the selector are provided. The method includes: providing a substrate; forming a lower electrode on the substrate, where the lower electrode is made of a metal, and the metal is made up of metal atoms which diffuse under an annealing condition of below 400° C.; forming a first metal oxide layer on the lower electrode; performing an annealing process on the first metal oxide layer to make the metal atoms in the lower electrode diffuse into the first metal oxide layer to form a first metal oxide layer doped with metal atoms; forming a second metal oxide layer on the first metal oxide layer doped with metal atoms; forming an upper electrode layer on the second metal oxide layer; and patterning the upper electrode layer to form an upper electrode.
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公开(公告)号：US20220172035A1
公开(公告)日：2022-06-02
申请号：US17310203
申请日：2019-01-28
Inventor： Hangbing LV , Xiaoxin XU , Qing LUO , Ming LIU
Abstract: Disclosed is a neural network operation device, including: an operation array including operation units, wherein each operation unit includes: a source terminal, a drain terminal, a gate electrode, a threshold voltage adjustment layer under the gate electrode, and a channel region extending between a source region and a drain region, the threshold voltage adjustment layer is located on the channel region. The gate electrodes of each column of operation units of the operation array are connected together, and each column is used to adjust a weight value according to a threshold voltage adjusted by the threshold voltage adjustment layer. The threshold voltage adjustment layer is a ferroelectric layer.
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公开(公告)号：US20200066984A1
公开(公告)日：2020-02-27
申请号：US16489266
申请日：2017-02-28
Inventor： Qi LIU , Xiaolong ZHAO , Sen LIU , Ming LIU , Hangbing LV , Shibing LONG , Yan WANG , Facai WU
IPC: H01L45/00
Abstract: The present disclosure provides a conductive bridge semiconductor device and a method of manufacturing the same. The conductive bridge semiconductor device includes a lower electrode, a resistive switching functional layer, an ion barrier layer and an active upper electrode from bottom to top, wherein the ion barrier layer is provided with certain holes through which active conductive ions pass. Based on this structure, the precise designing of the holes on the barrier layer facilitates the modulation of the quantity, size and density of the conduction paths in the conductive bridge semiconductor device, which enables that the conductive bridge semiconductor device can be modulated to be a nonvolatile conductive bridge resistive random access memory or a volatile conductive bridge selector. Based on the above method, ultra-low power nonvolatile conductive bridge memory and high driving-current volatile conductive bridge selector with controllable polarity are completed.
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Patent Agency Ranking
6.发明申请公开(公告)号：US20200335165A1
公开(公告)日：2020-10-22
申请号：US16959225
申请日：2018-01-22
Inventor： Qi LIU , Wei WANG , Sen LIU , Feng ZHANG , Hangbing LV , Shibing LONG , Ming LIU
Abstract: An operation method for integrating logic calculations and data storage based on a crossbar array structure of resistive switching devices. The calculation and storage functions of the method are based on the same hardware architecture, and the data storage is completed while performing calculation, thereby realizing the fusion of calculation and storage. The method includes applying a pulse sequence to a specified word line or bit line by a controller, configuring basic units of resistive switching devices to form different serial-parallel structures, such that three basic logic operations, i.e. NAND, OR, and COPY, are implemented and mutually combined on this basis, thereby implementing 16 types of binary Boolean logic and full addition operations, and on this basis, a method for implementing a parallel logic and full addition operations is provided.
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7.发明申请公开(公告)号：US20190006584A1
公开(公告)日：2019-01-03
申请号：US16064120
申请日：2016-08-12
Inventor： Nianduan LU , Pengxiao SUN , Ling LI , Ming IIU , Qi LIU , Hangbing LV , Shibing LONG
IPC: H01L45/00
Abstract: A method for improving endurance of 3D integrated resistive switching memory, comprising: Step 1: Calculating the temperature distribution in the integrated array by the 3D Fourier heat conduction equation; Step 2, selecting heat transfer mode; Step 3: selecting an appropriate array structure; Step 4: analyzing the influence of integration degree on temperature in the array; Step 5: evaluating the endurance performance in the array; and Step 6: changing the array parameters according to the evaluation result to improve the endurance performance. According to the method of the present invention, based on the thermal transmission mode in the 3D integrated resistive switching device, a suitable 3D integrated array is selected to analyze the influence of the integration degree on the device temperature so as to evaluate and improve the endurance of the 3D integrated resistive switching device.
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公开(公告)号：US20170352806A1
公开(公告)日：2017-12-07
申请号：US15539608
申请日：2014-12-26
Inventor： Hangbing LV , Ming LIU , Qi LIU , Shibing LONG
CPC classification number: H01L45/1206 , H01L27/2481 , H01L45/00 , H01L45/124 , H01L45/141 , H01L45/147 , H01L45/1608 , H01L45/1675 , H01L45/1683
Abstract: There is provided a three-terminal atomic switching device and a method of manufacturing the same, which belongs to the field of microelectronics manufacturing and memory technology. The three-terminal atomic switching device includes: a stack structure including a source terminal and a drain terminal; a vertical trench formed by etching the stack structure; an M8XY6 channel layer formed on an inner wall and a bottom of the vertical trench; and a control terminal formed on a surface of the M8XY6 channel layer, wherein the control terminal fills the vertical trench. The source terminal resistance and the drain terminal resistance are controlled by the control terminal. The invention is based on the three-terminal atomic switching device, and realizes high switching ratio characteristic, simple structure, easy integration, high density and low cost due to high non-linearity of the source-drain resistance with respect to the control terminal voltage, and thus can be used in a gated device in a cross-array structure to inhibit a crosstalk phenomenon caused by the leakage current. The three-terminal atomic switching device proposed by the invention is suitable for a planar stacked cross-array structure and a vertical cross-array structure, so as to realize high-density three-dimensional storage.
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公开(公告)号：US20240023469A1
公开(公告)日：2024-01-18
申请号：US18254981
申请日：2020-12-14
Inventor： Xiaoxin XU , Xiaoyan LI , Danian DONG , Jie YU , Hangbing LV
CPC classification number: H10N70/8833 , H10N70/026 , H10N70/841 , H10N70/023 , G11C13/0007
Abstract: The present disclosure provides a resistive random access memory and a method of preparing the same. The resistive random access memory includes: a resistive layer, an upper electrode and a barrier structure. The resistive layer is arranged on a substrate; the upper electrode is arranged on the resistive layer; and the barrier structure is arranged between the resistive layer and the upper electrode, and the barrier structure is configured for electrons to pass through a conduction band of the barrier structure when a device performs an erasing operation, so as to avoid forming of a defect in the resistive layer and causing a reverse breakdown of the resistive layer.
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公开(公告)号：US20220122997A1
公开(公告)日：2022-04-21
申请号：US17310282
申请日：2019-01-28
Inventor： Hangbing LV , Qing LUO , Xiaoxin XU , Tiancheng GONG , Ming LIU
IPC: H01L27/1159 , H01L27/11597 , H01L25/065
Abstract: Disclosed is a memory, including a plurality of memory units, wherein each memory unit includes: a bulk substrate; a source electrode, a drain electrode and a channel region extending between a source region and a drain region that are located on the bulk substrate; a deep-level defect dielectric layer on the channel region; and a gate electrode on the deep-level defect dielectric layer. The memory of the present disclosure allows the memory unit to operate in the charge trapping mode and the polarization inversion mode. Therefore, the memory has functions of both DRAM and NAND, and combines the advantages of the two.
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