公开(公告)号：US20250081530A1

公开(公告)日：2025-03-06

申请号：US18725967

申请日：2023-11-27

Applicant: INSTITUTE OF MICROELECTRONICS, CHINESE ACADEMY OF SCIENCES

Inventor： Junjie LI ,  Enxu LIU ,  Na ZHOU ,  Jianfeng GAO ,  Junfeng LI ,  Yongliang LI ,  Jun LUO ,  Wenwu WANG

IPC: H01L29/423 ,  H01L21/3065 ,  H01L21/762 ,  H01L21/8238 ,  H01L27/092 ,  H01L29/06 ,  H01L29/08 ,  H01L29/66 ,  H01L29/775 ,  H01L29/786

Abstract: A semiconductor device and a method for manufacturing the same. The method comprises: providing a substrate; forming a fin, a dummy gate, a first spacer, and a hard mask on a surface of the substrate; etching the substrate to form a groove located directly beneath the fin and running through a second spacer; forming, in the groove, a filling layer made of an insulating dielectric material, and thermal conductivity of the insulating dielectric material is higher than that of the substrate; removing the second spacer through etching; removing two opposite ends of each sacrificial layer to form cavities; filling the cavities to form inner spacers; forming a source and a drain on the substrate; forming a first dielectric layer; planarizing the first dielectric layer to expose the dummy gate; removing the dummy gate to release a channel comprising conductive nanosheets; forming a surrounding gate surrounding the conductive nanosheets.

公开(公告)号：US20250089357A1

公开(公告)日：2025-03-13

申请号：US18822794

申请日：2024-09-03

Applicant: INSTITUTE OF MICROELECTRONICS, CHINESE ACADEMY OF SCIENCES

Inventor： Yongliang LI ,  Huaizhi LUO

IPC: H01L27/092 ,  H01L21/28 ,  H01L21/8238 ,  H01L29/06 ,  H01L29/423 ,  H01L29/66 ,  H01L29/775 ,  H01L29/786

Abstract: The semiconductor device includes a semiconductor substrate; and a first gate-all-around transistor and a second gate-all-around transistor formed on the semiconductor substrate and spaced apart from each other in a direction parallel to a surface of the semiconductor substrate. Each of the first gate-all-around transistor and the second gate-all-around transistor includes at least one nanostructure layer between a source region and a drain region. The nanostructure layer in the first gate-all-around transistor and the nanostructure layer in the second gate-all-around transistor are integrally formed. A thickness of each part of each nanostructure layer in the first gate-all-around transistor in a length direction of the nanostructure layer is less than a thickness of a corresponding nanostructure layer in the second gate-all-around transistor. A thickness of a gate stack in the first gate-all-around transistor is greater than a thickness of a gate stack in the second gate-all-around transistor.

公开(公告)号：US20250006813A1

公开(公告)日：2025-01-02

申请号：US18754572

申请日：2024-06-26

Applicant: INSTITUTE OF MICROELECTRONICS, CHINESE ACADEMY OF SCIENCES

Inventor： Yongliang LI ,  Fei ZHAO

IPC: H01L29/423 ,  H01L21/8234 ,  H01L27/088 ,  H01L29/06 ,  H01L29/66 ,  H01L29/775 ,  H01L29/786

Abstract: A transistor and a manufacturing method. The transistor includes a semiconductor base substrate, an active structure, a dielectric structure, and a gate stack structure. The active structure is formed on the semiconductor base substrate. The active structure includes a source region, a drain region, and a channel region located between the source region and the drain region. The channel region includes at least two nanostructures stacked in a thickness direction of the semiconductor base substrate. In the channel region, a bottom nanostructure has a greater width than other nanostructures. The dielectric structure is formed between the semiconductor base substrate and the active structure. The dielectric structure is in contact with the bottom nanostructure. The gate stack structure is formed on a surface of the bottom nanostructure not in contact with the dielectric structure, and the gate stack surrounds a periphery of the other nanostructures.

公开(公告)号：US20210151557A1

公开(公告)日：2021-05-20

申请号：US16824761

申请日：2020-03-20

Applicant: INSTITUTE OF MICROELECTRONICS, CHINESE ACADEMY OF SCIENCES

Inventor： Yongliang LI ,  Xiaohong CHENG ,  Qingzhu ZHANG ,  Huaxiang YIN ,  Wenwu WANG

IPC: H01L29/06 ,  H01L29/417 ,  H01L29/66 ,  H01L29/78 ,  H01L21/8234

Abstract: A semiconductor device, including: a silicon substrate; multiple fin structures, formed on the silicon substrate, where each extends along a first direction; a shallow trench insulator, located among the multiple fin structures; a gate stack, intersecting with the multiple fin structures and extending along a second direction, where first spacers are formed on two sidewalls in the first direction of the gate stack; source-or-drain regions, formed on the multiple fin structures, and located at two sides of the gate stack along the first direction; and a channel region, including a portion of the multiple fin structures located between the first spacers. and notch structures. A notch structure recessed inward is located between each of the multiple fin structures and the silicon substrate. The notch structure includes an isolator that isolates each of the multiple fin structures from the silicon substrate.

公开(公告)号：US20240379764A1

公开(公告)日：2024-11-14

申请号：US18533891

申请日：2023-12-08

Applicant: INSTITUTE OF MICROELECTRONICS, CHINESE ACADEMY OF SCIENCES

Inventor： Yongliang LI ,  Fei ZHAO

IPC: H01L29/10 ,  H01L29/06 ,  H01L29/423 ,  H01L29/66 ,  H01L29/775

Abstract: A gate-all-around transistor and a method for manufacturing the same. The gate-all-around transistor comprises: a semiconductor substrate; an active structure disposed on the semiconductor substrate, where the active structure comprises a source, a drain, and a channel between the source and the drain; a doped epitaxial structure, where a portion of the semiconductor substrate beneath the channel is recessed to form a first groove, the first groove is fully filled with the doped epitaxial structure, and primary carriers of the doped epitaxial structure are opposite in polarity to primary carriers of the source and the drain; and a gate stack structure surrounding the channel, where a portion of the gate stack structure beneath the channel is disposed between the doped epitaxial structure and the channel.

公开(公告)号：US20210151561A1

公开(公告)日：2021-05-20

申请号：US16824810

申请日：2020-03-20

Applicant: INSTITUTE OF MICROELECTRONICS, CHINESE ACADEMY OF SCIENCES

Inventor： Yongliang LI ,  Xiaohong CHENG ,  Qingzhu ZHANG ,  Huaxiang YIN ,  Wenwu WANG

IPC: H01L29/06 ,  H01L29/423 ,  H01L29/66 ,  H01L21/8234 ,  H01L21/84

Abstract: A stacked nanowire or nanosheet gate-all-around device, including: a silicon substrate; stacked nanowires or nanosheets located on the silicon substrate, extending along a first direction gate stacks and including multiple nanowires or nanosheets that are stacked; a gate stack, surrounding each of the stacked nanowires or nanosheets, and extending along a second direction, where first spacers are located on two sidewalls of the gate stack in the first direction; source-or-drain regions, located at two sides of the gate stack along the first direction; a channel region, including a portion of the stacked nanowires or nanosheets that is located between the first spacers. A notch structure recessed inward is located between the stacked nanowires or nanosheets and the silicon substrate, and includes an isolator that isolates the stacked nanowires or nanosheets from the silicon substrate. A method for manufacturing the stacked nanowire or nanosheet gate-all-around device is further provided.

公开(公告)号：US20210125873A1

公开(公告)日：2021-04-29

申请号：US16924057

申请日：2020-07-08

Applicant: INSTITUTE OF MICROELECTRONICS, CHINESE ACADEMY OF SCIENCES

Inventor： Yongliang LI ,  Hong YANG ,  Xiahong CHENG ,  Xiaolei WANG ,  Xueli MA ,  Wenwu WANG

IPC: H01L21/8234 ,  H01L29/66 ,  H01L29/775 ,  H01L29/78 ,  H01L21/308 ,  H01L29/06 ,  H01L29/165 ,  H01L29/51 ,  H01L21/02

Abstract: The disclosure provides a method for fabricating a semiconductor device, in which a core device of the semiconductor device employs a stacked nanowires or nanosheets structure, and an input/output device of the semiconductor device employs FinFET structure. The disclosure also provides a FinFET with an input/output device compatible with the stacked nanowires or nanosheets. The solution of the disclosure solves the problem that if the input/output device employs stacked nanowires or nanosheets device, it is difficult to fill a metal gate between two nanowires or nanosheets due to the thicker dielectric layer, and even if the metal gate is filled partially, the electrical performance of the input/output device is still poor.