公开(公告)号：US20160240382A1

公开(公告)日：2016-08-18

申请号：US14407210

申请日：2013-08-30

Applicant: INSTITUTE OF MICROELECTRONICS, CHINESE ACADEMY OF SCIENCES

Inventor： Hong YANG ,  Wenwu WANG ,  Jiang YAN ,  Weichun LUO

IPC: H01L21/28 ,  H01L21/8238 ,  H01L29/51 ,  H01L21/321

CPC classification number: H01L21/28088 ,  H01L21/321 ,  H01L21/823842 ,  H01L29/517 ,  H01L29/66545

Abstract: A method for adjusting an effective work function of a metal gate. The method includes forming a metal gate arrangement comprising at least a metal work function layer, and performing plasma treatment on at least one layer in the metal gate arrangement. In this way, it is possible to adjust the effective work function of the metal gate in a relatively flexible way.

Abstract translation: 一种用于调节金属门的有效功函数的方法。 该方法包括形成包括至少金属功函数层的金属栅极布置，并且对金属栅极布置中的至少一层进行等离子体处理。 以这种方式，可以以相对灵活的方式调整金属门的有效功能。

公开(公告)号：US20160086946A1

公开(公告)日：2016-03-24

申请号：US14721386

申请日：2015-05-26

Applicant: INSTITUTE OF MICROELECTRONICS, CHINESE ACADEMY OF SCIENCES

Inventor： Huaxiang YIN ,  Hong YANG ,  Qingzhu ZHANG ,  Qiuxia XU

IPC: H01L27/092 ,  H01L21/8238

CPC classification number: H01L27/092 ,  H01L21/823821 ,  H01L21/823828 ,  H01L21/823842 ,  H01L27/0924

Abstract: An CMOS device comprises a plurality of NMOS transistors and a plurality of PMOS transistors, each of which comprises a gate stack constituted of a gate insulating layer and a gate metal layer on a substrate, a source/drain region in the substrate on both sides of the gate stack and a channel region below the gate stack, wherein the gate metal layer of each NMOS transistor comprising a first barrier layer, an NMOS work function adjusting layer, a second barrier layer, and a filling layer, and wherein the gate metal layer of each PMOS transistor comprising a first barrier layer, a PMOS work function adjusting layer, an NMOS work function adjusting layer, a second barrier layer, and a filling layer, and wherein the first barrier layer in the gate metal layer of the NMOS transistor and the first barrier layer in the gate metal layer of the PMOS transistor contain a doping ion to finely adjust the work function. The semiconductor device and the method for manufacturing the same according to the present disclosure utilize the sacrificial layer to diffuse impurity to the barrier layer so that the adjusting accuracy of the threshold voltage may be effectively improved, thereby facilitating in improving the whole performance of the device.

Abstract translation: CMOS器件包括多个NMOS晶体管和多个PMOS晶体管，每个PMOS晶体管包括由衬底上的栅极绝缘层和栅极金属层构成的栅极堆叠，在衬底的两侧的衬底中的源极/漏极区域 栅极堆叠和栅极堆叠下方的沟道区，其中每个NMOS晶体管的栅极金属层包括第一势垒层，NMOS功函数调节层，第二势垒层和填充层，并且其中栅极金属层 每个PMOS晶体管包括第一阻挡层，PMOS功函数调整层，NMOS功函数调整层，第二势垒层和填充层，并且其中NMOS晶体管的栅极金属层中的第一势垒层和 PMOS晶体管的栅极金属层中的第一势垒层含有掺杂离子以微调功函数。 根据本公开的半导体器件及其制造方法利用牺牲层将杂质扩散到阻挡层，从而可以有效地提高阈值电压的调整精度，从而有助于提高器件的整体性能 。

公开(公告)号：US20210125873A1

公开(公告)日：2021-04-29

申请号：US16924057

申请日：2020-07-08

Applicant: INSTITUTE OF MICROELECTRONICS, CHINESE ACADEMY OF SCIENCES

Inventor： Yongliang LI ,  Hong YANG ,  Xiahong CHENG ,  Xiaolei WANG ,  Xueli MA ,  Wenwu WANG

IPC: H01L21/8234 ,  H01L29/66 ,  H01L29/775 ,  H01L29/78 ,  H01L21/308 ,  H01L29/06 ,  H01L29/165 ,  H01L29/51 ,  H01L21/02

Abstract: The disclosure provides a method for fabricating a semiconductor device, in which a core device of the semiconductor device employs a stacked nanowires or nanosheets structure, and an input/output device of the semiconductor device employs FinFET structure. The disclosure also provides a FinFET with an input/output device compatible with the stacked nanowires or nanosheets. The solution of the disclosure solves the problem that if the input/output device employs stacked nanowires or nanosheets device, it is difficult to fill a metal gate between two nanowires or nanosheets due to the thicker dielectric layer, and even if the metal gate is filled partially, the electrical performance of the input/output device is still poor.

公开(公告)号：US20180294342A1

公开(公告)日：2018-10-11

申请号：US15871690

申请日：2018-01-15

Applicant: INSTITUTE OF MICROELECTRONICS, CHINESE ACADEMY OF SCIENCES

Inventor： Jinjuan XIANG ,  Xiaolei WANG ,  Hong YANG ,  Shi LIU ,  Junfeng LI ,  Wenwu WANG ,  Chao ZHAO

IPC: H01L29/66 ,  H01L29/49 ,  H01L21/265

CPC classification number: H01L29/66545 ,  H01L21/265 ,  H01L29/4966

Abstract: The present disclosure provides a method for manufacturing a transistor having a gate with a variable work function, comprising: providing a semiconductor substrate; forming a dummy gate stack on the semiconductor substrate and performing ion implantation on an exposed area of the semiconductor substrate at both sides of the dummy gate stack to form source/drain regions; removing the dummy gate and annealing the source/drain regions; providing an atomic layer deposition reaction device; introducing a precursor source reactant into the atomic layer deposition reaction device; and controlling an environmental factor for the atomic layer deposition device to grow a work function metal layer. The present disclosure also provides a transistor having a gate with a variable work function. The present disclosure may adjust a variable work function, and may use the same material system to obtain an adjustable threshold voltage within an adjustable range.