公开(公告)号：GB2520850A

公开(公告)日：2015-06-03

申请号：GB201500359

申请日：2013-06-06

Applicant: INTEL CORP

Inventor： BHANDARU MALINI K ,  BACE MATTHEW M ,  BROWN A LEONARD ,  STEINER IAN M ,  GARG VIVEK ,  DEHAEMER ERIC J ,  BOBHOLZ SCOTT P

IPC: G06F11/34 ,  G06F1/32

Abstract: A processor is described that includes a processing core and a plurality of counters for the processing core. The plurality of counters are to count a first value and a second value for each of multiple threads supported by the processing core. The first value reflects a number of cycles at which a non sleep state has been requested for the first value's corresponding thread, and, a second value that reflects a number of cycles at which a non sleep state and a highest performance state has been requested for the second value's corresponding thread. The first value's corresponding thread and the second value's corresponding thread being a same thread.