公开(公告)号：GB2520850A

公开(公告)日：2015-06-03

申请号：GB201500359

申请日：2013-06-06

Applicant: INTEL CORP

Inventor： BHANDARU MALINI K ,  BACE MATTHEW M ,  BROWN A LEONARD ,  STEINER IAN M ,  GARG VIVEK ,  DEHAEMER ERIC J ,  BOBHOLZ SCOTT P

IPC: G06F11/34 ,  G06F1/32

Abstract: A processor is described that includes a processing core and a plurality of counters for the processing core. The plurality of counters are to count a first value and a second value for each of multiple threads supported by the processing core. The first value reflects a number of cycles at which a non sleep state has been requested for the first value's corresponding thread, and, a second value that reflects a number of cycles at which a non sleep state and a highest performance state has been requested for the second value's corresponding thread. The first value's corresponding thread and the second value's corresponding thread being a same thread.

公开(公告)号：GB2518101A

公开(公告)日：2015-03-11

申请号：GB201500049

申请日：2013-06-27

Applicant: INTEL CORP

Inventor： BHANDARU MALINI K ,  DEHAEMER ERIC J ,  MAKARAM RAGHUNANDAN ,  GARG VIVEK ,  BOBHOLZ SCOTT P

IPC: G06F1/32

Abstract: In one embodiment, a multicore processor includes cores that can independently execute instructions, each at an independent voltage and frequency. The processor may include a power controller having logic to provide for configurability of power management features of the processor. One such feature enables at least one core to operate at an independent performance state based on a state of a single power domain indicator present in a control register. Other embodiments are described and claimed.