公开(公告)号：JP2013225318A

公开(公告)日：2013-10-31

申请号：JP2013112958

申请日：2013-05-29

Applicant: Intel Corp ,  インテル・コーポレーション

Inventor： SMELYANSKIY MIKHAIL ,  CHEN YEN-KUANG ,  LEE VICTOR W ,  DASIKA GANESH S ,  GONZALEZ JOSE ,  KIM CHANGKYU ,  CHHUGANI JATIN ,  GAGO JULIO ,  GALAN SANTIAGO ,  DEL BARRIO VICTOR MOYA

IPC: G06T15/04

CPC classification number: G06T15/04 ,  G06T7/60 ,  G06T11/001 ,  G06T15/005

Abstract: PROBLEM TO BE SOLVED: To provide a texture unit that optimizes texture filtering.SOLUTION: The efficiency of communication between a processor core and a texture unit may be improved by reducing the computational overhead caused by the core in encoding groups of pixels to be textured. A region or group of pixels may be textured as a unit, using a range specifier and one or more anchor pixels to define the group. In some embodiments, processing efficiency of grouped pixels is improved.

Abstract translation: 要解决的问题：提供优化纹理过滤的纹理单元。解决方案：通过减少由编码要纹理化的像素组中的核心引起的计算开销，可以提高处理器核心和纹理单元之间的通信效率。 可以使用范围说明符和一个或多个定位像素来定义区域或一组像素作为单元进行纹理化。 在一些实施例中，改进了分组像素的处理效率。

公开(公告)号：JP2011134317A

公开(公告)日：2011-07-07

申请号：JP2010268453

申请日：2010-12-01

Applicant: Intel Corp ,  インテル・コーポレーション

Inventor： SMELYANSKIY MIKHAIL ,  CHEN YEN-KUANG ,  LEE VICTOR W ,  DASIKA GANESH S ,  GONZALEZ JOSE ,  KIM CHANGKYU ,  CHHUGANI JATIN ,  GAGO JULIO ,  GALAN SANTIAGO ,  DEL BARRIO VICTOR MOYA

IPC: G06T15/04

CPC classification number: G06T15/04 ,  G06T7/60 ,  G06T11/001 ,  G06T15/005

Abstract: PROBLEM TO BE SOLVED: To provide a texture unit that optimizes texture filtering and performs texture filtering faster than a general purpose processor. SOLUTION: A region or group of pixels may be textured as a unit, using a range specifier and one or more anchor pixels to define the group. Processing grouped pixels improves efficiency. COPYRIGHT: (C)2011,JPO&INPIT

Abstract translation: 要解决的问题：提供优化纹理过滤并且比通用处理器更快地执行纹理过滤的纹理单元。 解决方案：可以使用范围说明符和一个或多个锚点像素来定义区域或一组像素作为单元进行纹理化。 处理分组的像素可提高效率。 版权所有（C）2011，JPO＆INPIT

公开(公告)号：WO2009120981A2

公开(公告)日：2009-10-01

申请号：PCT/US2009038596

申请日：2009-03-27

Applicant: INTEL CORP ,  SMELYANSKIY MIKHAIL ,  KUMAR SANJEEV ,  KIM DAEHYUN ,  LEE VICTOR W ,  NGUYEN ANTHONY D ,  CHEN YEN-KUANG ,  HUGHES CHRISTOPHER ,  KIM CHANGKYU ,  CHHUGANI JATIN

Inventor： SMELYANSKIY MIKHAIL ,  KUMAR SANJEEV ,  KIM DAEHYUN ,  LEE VICTOR W ,  NGUYEN ANTHONY D ,  CHEN YEN-KUANG ,  HUGHES CHRISTOPHER ,  KIM CHANGKYU ,  CHHUGANI JATIN

IPC: G06F9/38 ,  G06F9/445 ,  G06F15/80

CPC classification number: G06F9/30036 ,  G06F9/30018 ,  G06F9/30021 ,  G06F9/30032 ,  G06F9/3004 ,  G06F9/30043 ,  G06F9/30087 ,  G06F9/3834 ,  G06F9/3885 ,  G06K9/6212 ,  G06T5/40 ,  H04N1/4074

Abstract: In one embodiment, a processor may include a vector unit to perform operations on multiple data elements responsive to a single instruction, and a control unit coupled to the vector unit to provide the data elements to the vector unit, where the control unit is to enable an atomic vector operation to be performed on at least some of the data elements responsive to a first vector instruction to be executed under a first mask and a second vector instruction to be executed under a second mask. Other embodiments are described and claimed.

Abstract translation: 在一个实施例中，处理器可以包括向量单元，用于响应于单个指令对多个数据元素执行操作;以及控制单元，耦合到向量单元，以将数据元素提供给向量单元，其中控制单元将使能 响应于在第一掩模下执行的第一向量指令和在第二掩码下执行的第二向量指令，对至少一些数据元素执行的原子向量操作。 描述和要求保护其他实施例。

公开(公告)号：GB2476552A

公开(公告)日：2011-06-29

申请号：GB201020913

申请日：2010-12-09

Applicant: INTEL CORP

Inventor： SMELYANSKIY MIKHAIL ,  GONZALEZ JOSE ,  GALAN SANTIAGO ,  CHEN YEN-KUANG ,  KIM CHANGKYU ,  BARRIO VICTOR MOYA DEL ,  LEE VICTOR W ,  CHHUGANI JATIN ,  DASIKA GANESH S ,  GAGO JULIO

IPC: G06T15/04 ,  G06T9/00

Abstract: A region or group of pixels may be textured as a unit, using a range specifier and one or more anchor pixels to define the group. The anchor pixels define a reference point for a geometric shape; say a rectangle and the range specifiers specify an offset from this point. The reference and the offset may be stored in a tuple that may include a geometric shape identifier. The decoding of such tuples to generate pixel addresses may be carried out using state machine and may involve the use of convolution or dot products.

公开(公告)号：DE102010055708A1

公开(公告)日：2012-05-10

申请号：DE102010055708

申请日：2010-12-22

Applicant: INTEL CORP

Inventor： KIM CHANGKYU ,  GUY STEPHEN J ,  NGUYEN ANTHONY-TRUNG D ,  KIM DAEHYUN ,  CHHUGANI JATIN

IPC: G06F17/10

Abstract: Ein Verfahren zum Berechnen einer kollisionsfreien Geschwindigkeit (117, 217) für einen Agenten (110) in einer Menschenmassensimulationsumgebung (100) umfasst das Identifizieren eines quadratischen Optimierungsproblems, das der kollisionsfreien Geschwindigkeit entspricht, und das Finden einer genauen Lösung für das quadratische Optimierungsproblem, indem ein geometrischer Ansatz verwendet wird.

公开(公告)号：DE102011014977A1

公开(公告)日：2011-10-27

申请号：DE102011014977

申请日：2011-03-24

Applicant: INTEL CORP

Inventor： CHHUGANI JATIN ,  CATANZARO BRYAN ,  KUMAR SANJEEV ,  KIM CHANGKYU

IPC: G06T15/00 ,  G06F17/30 ,  G06T1/60

Abstract: Ein Verfahren, um eine gesamte Rechenzeit für eine visuelle Simulationsschleife zu verringern, beinhaltet die gemeinsame Benutzung einer gemeinsamen Datenstruktur über jede Phase der visuellen Simulationsschleife durch die Anpassung der gemeinsamen Datenstruktur an eine Anforderung für jede spezielle Phase vor dem Ausführen einer Berechnung für diese spezielle Phase.

公开(公告)号：GB2476550A

公开(公告)日：2011-06-29

申请号：GB201020736

申请日：2010-12-07

Applicant: INTEL CORP

Inventor： BADER ALEKSEY A ,  SMELYANSKIY MIKHAIL ,  CHHUGANI JATIN

IPC: G06T1/20 ,  G06T1/60

Abstract: Parallel and vectored data structures may be used in a single instruction multiple data processor that applies the Gilbert-Johnson-Keerthi(GJK) algorithm. As a result, the performance of multi-core processors doing graphics processing may be increased in some cases. The data input to the SMID device is vectored and aligned for optimum processing. The application is aimed at determining the minimum distance between two displayed objects.

公开(公告)号：EP2751667A4

公开(公告)日：2015-07-15

申请号：EP11871468

申请日：2011-08-29

Applicant: INTEL CORP

Inventor： SEWALL JASON D ,  KIM CHANGKYA ,  CHHUGANI JATIN ,  SATISH NADATHUR RAJAGOPALAN

IPC: G06F9/38 ,  G06F9/06

CPC classification number: G06F17/30327 ,  G06F9/5005 ,  G06F2209/5018

Abstract: Embodiments of techniques and systems for parallel processing of B+ trees are described. A parallel B+ tree processing module with partitioning and redistribution may include a set of threads executing a batch of B+ tree operations on a B+ tree in parallel. The batch of operations may be partitioned amongst the threads. Next, a search may be performed to determine which leaf nodes in the B+ tree are to be affected by which operations. Then, the threads may redistribute operations between each other such that multiple threads will not operate on the same leaf node. The threads may then perform B+ tree operations on the leaf nodes of the B+ tree in parallel. Subsequent modifications to nodes in the B+ may similarly be redistributed and performed in parallel as the threads work up the tree.

Abstract translation: 描述了B +树的并行处理技术和系统的实施例。 具有分区和再分配的并行B +树处理模块可以包括一组在B +树上并行执行一批B +树操作的线程。 该批操作可以在线程之间进行分区。 接下来，可以执行搜索以确定B +树中的哪些叶节点将受哪个操作的影响。 然后，线程可以在彼此之间重新分配操作，使得多个线程将不在同一叶节点上操作。 然后，线程可以并行地在B +树的叶节点上执行B +树操作。 当线程处理树时，对B +中的节点的后续修改可以类似地重新分布并且并行执行。

公开(公告)号：GB2476550B

公开(公告)日：2013-10-30

申请号：GB201020736

申请日：2010-12-07

Applicant: INTEL CORP

Inventor： BADER ALEKSEY A ,  SMELYANSKIY MIKHAIL ,  CHHUGANI JATIN

IPC: G06T1/20 ,  G06T1/60

公开(公告)号：GB2479047A

公开(公告)日：2011-09-28

申请号：GB201104574

申请日：2011-03-17

Applicant: INTEL CORP

Inventor： CHHUGANI JATIN ,  CATANZARO BRYAN ,  KUMAR SANJEEV ,  KIM CHANGKYU ,  SATISH NADATHUR RAJAGOPALAN

IPC: G06T15/00 ,  G06T1/20

Abstract: A method for handling data structures for visual simulation loops to facilitate graphics rendering in a virtual scene includes the steps of building a data structure for a first phase/stage of the loop, performing a 1stphase computation using said data structure, adapting (414) the data structure for a second phase of the loop and performing (413) a 2ndphase computation using the adapted data structure. The method enables a common data structure to be shared (410) for all phases/stages of a visual simulation loop wherein the data structure may be adapted/optimized as required for a particular computational phase. The data structure may comprise akd-tree, a bounding volume hierarchy (BVH) or a bounding interval hierarchy (BIH). By using and selectively adapting a common data structure, the total computational time required for the visual simulation loop may be reduced.