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    Message distribution technology on point-to-point mutual connection
    1.
    发明专利
    Message distribution technology on point-to-point mutual connection 有权
    点到点相互连接的消息分发技术

    公开(公告)号：JP2006134286A

    公开(公告)日：2006-05-25

    申请号：JP2005034392

    申请日：2005-02-10

    Applicant: Intel Corp ,  インテル コーポレイション

    Inventor： TIRUVALLUR KESHAVAN K ,  CRETA KENNETH C ,  BLANKENSHIP ROBERT G

    IPC: G06F13/36

    CPC classification number: G06F13/36

    Abstract: PROBLEM TO BE SOLVED: To provide a technology for distributing a message via a point-to-point network.
    SOLUTION: In embodiment of this invention, a message is distributed between electronic components inside the point-to-point mutual connection. This system is constructed of a first bus agent, which is arranged on a first bus for transmitting a broadcast message to one or more bus agents arranged on one or more buses except the first bus, and a second bus agent arranged on a second bus for receiving the broadcast message and notifying receipt of the broadcast message to the first bus agent.
    COPYRIGHT: (C)2006,JPO&NCIPI

    Abstract translation: 要解决的问题：提供一种通过点对点网络分发消息的技术。 解决方案：在本发明的实施例中，消息分布在点对点相互连接内的电子部件之间。 该系统由第一总线代理构成，其布置在第一总线上，用于将广播消息发送到布置在除了第一总线之外的一个或多个总线上的一个或多个总线代理，以及布置在第二总线上的第二总线代理 接收广播消息并通知广播消息的接收到第一总线代理。 版权所有（C）2006，JPO＆NCIPI

    Separating transactions into different virtual channels
    2.
    发明专利
    Separating transactions into different virtual channels 审中-公开
    将交易分为不同的虚拟通道

    公开(公告)号：JP2005318495A

    公开(公告)日：2005-11-10

    申请号：JP2004259773

    申请日：2004-09-07

    Applicant: Intel Corp ,  インテル コーポレイション

    Inventor： CRETA KENNETH C ,  SPINK AARON T ,  BLANKENSHIP ROBERT G

    IPC: H04L29/00 ,  G06F13/12 ,  G06F13/36 ,  G06F13/376 ,  G06F15/16

    CPC classification number: G06F13/36 ,  G06F13/12

    Abstract: PROBLEM TO BE SOLVED: To realize transfer of a transaction without dead lock through a system present for a number of system components of different protocols.
    SOLUTION: In one embodiment of the present invention, a method may include a step for separating an input transaction to an agent of a coherent system into at least first, second and third channels on the basis of a type of the input transaction. The input transaction may be sent by an equal apparatus connected to the coherent system. The transaction is separated on the basis of the type, so that dead locks may be avoided.
    COPYRIGHT: (C)2006,JPO&NCIPI

    Abstract translation: 要解决的问题：通过针对不同协议的多个系统组件存在的系统来实现没有死锁的事务的传送。 解决方案：在本发明的一个实施例中，一种方法可以包括基于输入事务的类型将输入事务分离为至少第一，第二和第三信道的代理的相干系统的代理的步骤 。 输入事务可以由连接到相干系统的相等设备发送。 交易根据类型分开，以便可以避免死锁。 版权所有（C）2006，JPO＆NCIPI

    Bereitstellen eines gemeinsamen Caching-Agenten für ein Kern- und integriertes Ein-/Ausgabe-(IO)-Modul
    3.
    发明专利
    Bereitstellen eines gemeinsamen Caching-Agenten für ein Kern- und integriertes Ein-/Ausgabe-(IO)-Modul 未知

    公开(公告)号：DE112012005210B4

    公开(公告)日：2018-10-25

    申请号：DE112012005210

    申请日：2012-12-11

    Applicant: INTEL CORP

    Inventor： CRETA KENNETH C ,  BLANKENSHIP ROBERT G ,  LIU YEN-CHENG ,  SANTHANAKRISHNAN GEEYARPURAM N ,  SRINIVASA GANAPATI N ,  MUTHRANSANALLUR SRIDHAR ,  FAHIM BAHAA

    IPC: G06F9/46 ,  G06F9/06 ,  G06F12/08

    Abstract: Vorrichtung, umfassend:ein Mehrkernprozessor einschließlich einer Vielzahl von Kernen, ein gemeinsam benutzter Cache-Speicher, ein integriertes Ein-/Ausgabe-(IIO)-Modul, um eine Schnittstelle zwischen dem Mehrkernprozessor und wenigstens einem IO-Gerät herzustellen, das mit dem Mehrkernprozessor gekoppelt ist, und einen Caching-Agenten, wobei der Caching-Agent Kohärenz-Logik einschließt, um Cache-Kohärenz-Operationen für die Vielzahl von Kernen und das IIO-Modul auszuführen und kohärenten Zugriff in Bezug auf die Kerntransaktionen als auch die IO-Gerät-Transaktionen zu ermöglichen, wobei das IIO-Modul eine erste Warteschlange für gepostete Anforderungen und eine zweite Warteschlange für nicht gepostete Anforderungen aufweist und wobei das IIO-Modul eine PCI Express-Schnittstelle aufweist, wobei das IIO-Modul ferner eingerichtet ist, mittels der Anforderungen direkt auf den Cache-Speicher zuzugreifen,wobei der Caching-Agent derart eingerichtet ist, dass bei einem Cache-Speicher-Zugriff eine gepostete Anforderung einer nicht geposteten Anforderung vorausgeht.

    MEMORY READ REQUESTS PASSING MEMORY WRITES
    4.
    发明申请
    MEMORY READ REQUESTS PASSING MEMORY WRITES 审中-公开
    内存读取请求通过内存写入

    公开(公告)号：WO2006012289A2

    公开(公告)日：2006-02-02

    申请号：PCT/US2005022455

    申请日：2005-06-24

    Applicant: INTEL CORP ,  MUTHRASANALLUR SRIDHAR ,  CRETA KENNETH C

    Inventor： MUTHRASANALLUR SRIDHAR ,  CRETA KENNETH C

    IPC: G06F12/00 ,  G06F13/16

    CPC classification number: G06F13/1626

    Abstract: Memory read and write requests are received. The read is received in accordance with a communication protocol that has a transction ordering rule in which a memory read cannot pass a memory write. The memory read and write requests are forwarded to the first device in accordance with another communication protocol that has a transaction ordering rule in which a memory read may pass a memory write. The forwarded memory read request is allowed to pass the forwarded memory write request whenever a relaxed ordering flag in the received read request is asserted. Other embodiments are also described and claimed.

    Abstract translation: 内存读取和写入请求被接收。 读取是根据具有其中存储器读取不能通过存储器写入的转换排序规则的通信协议来接收的。 根据具有其中存储器读取可以通过存储器写入的事务排序规则的另一种通信协议，存储器读取和写入请求被转发到第一设备。 只要接收到的读取请求中的宽松排序标志被声明，就允许转发的存储器读取请求传递转发的存储器写入请求。 其他实施例也被描述和要求保护。

    POWER FAILURE MODE FOR A MEMORY CONTROLLER
    8.
    发明专利
    POWER FAILURE MODE FOR A MEMORY CONTROLLER 未知

    公开(公告)号：MY129551A

    公开(公告)日：2007-04-30

    申请号：MYPI9902510

    申请日：1999-06-17

    Applicant: INTEL CORP

    Inventor： CRETA KENNETH C

    IPC: G06F12/08 ,  G06F12/16 ,  G11C11/403 ,  G11C11/404 ,  G11C11/406 ,  G11C11/407

    Abstract: A POWER FAILURE MODE FOR A MEMORY CONTROLLER, SUCH AS A MEMORY CONTROLLER (200) USED IN AN INPUT/OUTPUT PROCESSOR, WHICH, WHEN THE MEMORY CONTROLLER HAS SYSTEM POWER, REFRESHES A MEMORY UNIT, SUCH AS AN SDRAM MEMORY UNIT (210), AS REQUIRED TO MAINTAIN THE MEMORY IMAGE. IN ONE EMBODIMENT, WHEN A POWER FAILURE OCCURS, THE MEMORY CONTROLLER (200) ISSUES A SELF-REFRESH COMMAND TO THE MEMORY, WHICH HAS BATTERY-BACKUP POWER. A PCI RESET SIGNAL MAY BE USED TO DETERMINE WHEN A POWER FAILURE HAS OCCURRED. THE SELF-REFRESH COMMAND PLACES THE MEMORY IN A SELF-REFRESH MODE, AND A PROGRAMMABLE LOGIC DEVICE MAY BE USED TO ENSURE THAT A CLOCK ENABLE SIGNAL INPUT TO THE MEMORY MAINTAINS THE SELF-REFRESH MODE. WHEN SYSTEM POWER RETURNS, THE MEMORY CONTROLLER (200) RESUMES REFRESHING THE MEMORY (210). MOST ILLUSTRATIVE DRAWING IS (FIGURE 5).

    POWER FAILURE MODE FOR A MEMORY CONTROLLER
    9.
    发明公开
    POWER FAILURE MODE FOR A MEMORY CONTROLLER 审中-公开
    电源故障模式FOR内存控制器

    公开(公告)号：EP1090342A4

    公开(公告)日：2002-02-06

    申请号：EP99927507

    申请日：1999-06-14

    Applicant: INTEL CORP

    Inventor： CRETA KENNETH C

    IPC: G06F12/08 ,  G11C11/403 ,  G11C11/404 ,  G11C11/406 ,  G11C11/407 ,  G06F1/30

    CPC classification number: G11C11/406 ,  G11C11/404

    Abstract: A power failure mode for a memory controller (200), such as a memory controller used in an input/output processor (100), which, when the memory controller has system power, refreshes a memory unit (210), such as an SDRAM memory unit, as required to maintain the memory image. In one embodiment, when a power failure occurs, the memory controller issues a self-refresh command to the memory, which has battery-backup power. A PCI reset signal may be used to determine when a power failure has occured. The self-refresh command places the memory in a self-refresh mode, and a programmable logic device may be used to ensure that a clock enable signal input to the memory maintains the self-refresh mode. When system power returns, the memory controller resumes refreshing the memory.

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