公开(公告)号：WO2004100357A3

公开(公告)日：2004-12-09

申请号：PCT/US2004008921

申请日：2004-03-24

Applicant: INTEL CORP

Inventor： JAUSSI JAMES ,  KENNEDY JOSEPH ,  MOONEY STEPHEN

IPC: H03F1/48 ,  H03F3/45 ,  H03K19/0175 ,  H03K19/0185

CPC classification number: H03F1/486 ,  H03F3/4521 ,  H03F2200/36 ,  H03K19/01759 ,  H03K19/018592

Abstract: An amplifier includes multiple stages. Early stages of the multi-stage amplifier have low gain and preserve bandwidth.

Abstract translation: 放大器包括多个阶段。 多级放大器的早期阶段具有低增益和保持带宽。

公开(公告)号：GB2433805A

公开(公告)日：2007-07-04

申请号：GB0625616

申请日：2006-12-27

Applicant: INTEL CORP

Inventor： O'MAHONY FRANK ,  CASPER BRYAN ,  JAUSSI JAMES ,  HAYCOCK MATTHEW ,  KENNEDY JOSEPH ,  MANSURI MOZHAGAN ,  MOONEY STEPHEN R

IPC: G06F13/40

Abstract: An integrated circuit 301 has an internal transmission line 315 which receives a signal from an external transmission line 305. No termination circuitry is used to terminate the external transmission line. The internal transmission line transmits the signal passively to two or more different circuits 331, 332 on the integrated circuit. The internal transmission line may be terminated 318 at the opposite end to the external transmission line. The impedance of the internal transmission line may be matched to that of the external line. The internal transmission line may be connected to the circuits using buffers. Two transmission lines may be used to transmit differential signals.

公开(公告)号：DE112005000895T5

公开(公告)日：2007-03-22

申请号：DE112005000895

申请日：2005-04-08

Applicant: INTEL CORP

Inventor： KENNEDY JOSEPH ,  MOONEY STEPHEN

IPC: G06F1/10 ,  H03L7/081

Abstract: In some embodiments, a chip includes a chip interface to accept a delay control signal from outside the chip. The chip also includes a controllable delay line to delay an input signal responsive to the delay control signal to provide an output signal with a particular phase relationship to the input signal. Other embodiments are described and claimed.

公开(公告)号：AT444555T

公开(公告)日：2009-10-15

申请号：AT04815495

申请日：2004-12-23

Applicant: INTEL CORP

Inventor： MOONEY STEPHEN ,  KENNEDY JOSEPH

IPC: G04G99/00 ,  G11C7/10 ,  G06F13/16

Abstract: In some embodiments, a chip includes first and second ports to provide first and second received data signals and first and second received strobe signal, respectively. An internal clock signal has a fixed phase relationship to the first received strobe signal and the second received strobe signal has an arbitrary phase relationship with the internal clock signal. First and second write blocks latch the first and second received data signals synchronously with the first and second received strobe signals, respectively. Other embodiments are described and claimed.

公开(公告)号：GB2433805B

公开(公告)日：2008-07-16

申请号：GB0625616

申请日：2006-12-27

Applicant: INTEL CORP

Inventor： O'MAHONY FRANK ,  CASPER BRYAN ,  JAUSSI JAMES ,  HAYCOCK MATTHEW ,  KENNEDY JOSEPH ,  MANSURI MOZHAGAN ,  MOONEY STEPHEN R

IPC: G06F13/40

Abstract: For one disclosed embodiment, an integrated circuit may comprise an internal transmission line in one or more layers of the integrated circuit. The internal transmission line may be coupled to receive a signal from an external transmission line at a first end of the internal transmission line without use of termination circuitry. The internal transmission line may transmit the signal passively to a second end of the internal transmission line. The integrated circuit may also comprise first circuitry having an input coupled to the internal transmission line at a first location of the internal transmission line to receive the signal and second circuitry having an input coupled to the internal transmission line at a second location of the internal transmission line to receive the signal. The second location may be different from the first location. Other embodiments are also disclosed.

公开(公告)号：DE102006061878A1

公开(公告)日：2007-08-30

申请号：DE102006061878

申请日：2006-12-28

Applicant: INTEL CORP

Inventor： O'MAHONY FRANK ,  CASPER BRYAN ,  JAUSSI JAMES ,  HAYCOCK MATTHEW ,  KENNEDY JOSEPH ,  MANSURI MOZHAGAN ,  MOONEY STEPHEN

IPC: H04L25/02

Abstract: For one disclosed embodiment, an integrated circuit may comprise an internal transmission line in one or more layers of the integrated circuit. The internal transmission line may be coupled to receive a signal from an external transmission line at a first end of the internal transmission line without use of termination circuitry. The internal transmission line may transmit the signal passively to a second end of the internal transmission line. The integrated circuit may also comprise first circuitry having an input coupled to the internal transmission line at a first location of the internal transmission line to receive the signal and second circuitry having an input coupled to the internal transmission line at a second location of the internal transmission line to receive the signal. The second location may be different from the first location. Other embodiments are also disclosed.