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    PASSIVE IMPEDANCE EQUALIZATION OF HIGH SPEED SERIAL LINKS
    2.
    发明申请
    PASSIVE IMPEDANCE EQUALIZATION OF HIGH SPEED SERIAL LINKS 审中-公开
    高速串行链路的被动阻抗均衡

    公开(公告)号：WO2007089885A3

    公开(公告)日：2007-11-15

    申请号：PCT/US2007002722

    申请日：2007-01-30

    Applicant: INTEL CORP ,  BANERJEE GAURAB ,  MOONEY STEPHEN

    Inventor： BANERJEE GAURAB ,  MOONEY STEPHEN

    IPC: H05K1/02 ,  H01L23/66 ,  H01P5/02 ,  H05K1/14

    CPC classification number: H05K1/025 ,  H01L23/66 ,  H01L2224/16 ,  H01L2924/01078 ,  H01L2924/10253 ,  H01L2924/15174 ,  H01L2924/15311 ,  H01L2924/3011 ,  H01P5/02 ,  H05K1/14 ,  H05K1/181 ,  H05K2201/044 ,  H05K2201/09736 ,  H05K2201/10689 ,  H05K2201/10734 ,  H01L2924/00

    Abstract: A passive impedance equalization network (250,255,260,265) for high speed serial links is described. The impedance equalization network may include at least one stepped impedance transformer near points of impedance discontinuities (205,225,210,230). The impedance discontinuities may be at an interface connection between two circuit boards. The impedance discontinuities on a circuit board may be at a die-package interface and/or a package-board interface. The stepped impedance transformer may be formed in a package trace, a board trace or both. Forming the stepped impedance transformers in the traces requires no modification to existing package/board design methodology or technology. The stepped impedance transformers can provide impedance matching over a range of frequencies. To account for modeling errors in the design of the stepped impedance transformers integrated circuits transmitting data over the serial link may include active circuitry to select an output/input impedance for transmitters/receivers. Other embodiments are otherwise disclosed herein.

    Abstract translation: 描述了用于高速串行链路的无源阻抗均衡网络（250,255,260,265）。 阻抗均衡网络可以包括在阻抗不连续点附近的至少一个阶梯式阻抗变压器（205,225,210,230）。 阻抗不连续性可能在两个电路板之间的接口连接处。 电路板上的阻抗不连续性可能在管芯封装接口和/或封装板接口处。 阶梯式阻抗变压器可以形成为封装迹线，板迹线或两者。 在走线中形成阶梯式阻抗变压器不需要修改现有的封装/电路板设计方法或技术。 阶梯式阻抗变压器可以在一定频率范围内提供阻抗匹配。 为了解决在阶梯式阻抗变压器的设计中的建模误差，通过串行链路传输数据的集成电路可能包括用于选择发射机/接收机的输出/输入阻抗的有源电路。 其他实施例在此另外公开。

    4.
    发明专利
    未知

    公开(公告)号：AT444555T

    公开(公告)日：2009-10-15

    申请号：AT04815495

    申请日：2004-12-23

    Applicant: INTEL CORP

    Inventor： MOONEY STEPHEN ,  KENNEDY JOSEPH

    IPC: G04G99/00 ,  G11C7/10 ,  G06F13/16

    Abstract: In some embodiments, a chip includes first and second ports to provide first and second received data signals and first and second received strobe signal, respectively. An internal clock signal has a fixed phase relationship to the first received strobe signal and the second received strobe signal has an arbitrary phase relationship with the internal clock signal. First and second write blocks latch the first and second received data signals synchronously with the first and second received strobe signals, respectively. Other embodiments are described and claimed.

    5.
    发明专利
    未知

    公开(公告)号：DE102006061878A1

    公开(公告)日：2007-08-30

    申请号：DE102006061878

    申请日：2006-12-28

    Applicant: INTEL CORP

    Inventor： O'MAHONY FRANK ,  CASPER BRYAN ,  JAUSSI JAMES ,  HAYCOCK MATTHEW ,  KENNEDY JOSEPH ,  MANSURI MOZHAGAN ,  MOONEY STEPHEN

    IPC: H04L25/02

    Abstract: For one disclosed embodiment, an integrated circuit may comprise an internal transmission line in one or more layers of the integrated circuit. The internal transmission line may be coupled to receive a signal from an external transmission line at a first end of the internal transmission line without use of termination circuitry. The internal transmission line may transmit the signal passively to a second end of the internal transmission line. The integrated circuit may also comprise first circuitry having an input coupled to the internal transmission line at a first location of the internal transmission line to receive the signal and second circuitry having an input coupled to the internal transmission line at a second location of the internal transmission line to receive the signal. The second location may be different from the first location. Other embodiments are also disclosed.

    6.
    发明专利
    未知

    公开(公告)号：DE112005000895T5

    公开(公告)日：2007-03-22

    申请号：DE112005000895

    申请日：2005-04-08

    Applicant: INTEL CORP

    Inventor： KENNEDY JOSEPH ,  MOONEY STEPHEN

    IPC: G06F1/10 ,  H03L7/081

    Abstract: In some embodiments, a chip includes a chip interface to accept a delay control signal from outside the chip. The chip also includes a controllable delay line to delay an input signal responsive to the delay control signal to provide an output signal with a particular phase relationship to the input signal. Other embodiments are described and claimed.

    Differential cascode current mode driver
    7.
    发明专利
    Differential cascode current mode driver 未知

    公开(公告)号：AU2002254452A1

    公开(公告)日：2002-10-28

    申请号：AU2002254452

    申请日：2002-03-29

    Applicant: INTEL CORP

    Inventor： MOONEY STEPHEN ,  MARTIN AARON

    IPC: H03K19/017 ,  H03K19/0185 ,  H04L25/02 ,  H03F1/22

    Abstract: A current mode driver includes a tail current device, a differential pair of input transistors, cascode output transistors, and pre-charge circuits to charge cascode nodes between the differential pair of input transistors and the cascode output transistors. The current mode driver is driven by CMOS drivers that alternately turn the input transistors on and off. A wide-swing bias circuit provides bias voltages for the current mode driver. This bias voltage for the tail current device is closely matched to provide current matching between the bias circuit and the current mode driver.

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