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公开(公告)号：WO2004100357A3
公开(公告)日：2004-12-09
申请号：PCT/US2004008921
申请日：2004-03-24
Applicant: INTEL CORP
Inventor： JAUSSI JAMES , KENNEDY JOSEPH , MOONEY STEPHEN
IPC: H03F1/48 , H03F3/45 , H03K19/0175 , H03K19/0185
CPC classification number: H03F1/486 , H03F3/4521 , H03F2200/36 , H03K19/01759 , H03K19/018592
Abstract: An amplifier includes multiple stages. Early stages of the multi-stage amplifier have low gain and preserve bandwidth.
Abstract translation: 放大器包括多个阶段。 多级放大器的早期阶段具有低增益和保持带宽。
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公开(公告)号：WO2004098048A3
公开(公告)日：2005-03-10
申请号：PCT/US2004009031
申请日：2004-03-24
Applicant: INTEL CORP
Inventor： JAUSSI JAMES
CPC classification number: H03G1/0088 , H03F3/45183 , H03F2203/45466 , H03F2203/45641 , H03G1/0023
Abstract: The application discloses a differential amplifier with selectable gain. The differential amplifier comprises a pair of input transistors, a first pair of load transistors and a second pair of load transistors. The drain-source-paths of the first pair of load transistors is connected between a reference potential and the two output terminals of the pair of input transistors, while the gates are commonly connected to a control voltage. The drain-source-paths of the second pair of load transistors os connected in parallel to the drain-source-paths of the first pair of load transistors. Through a control circuit, the gates of the second pair of load transistors are either connected to the reference potential (second pair deactivated) or cross coupled to the output terminals of the pair of input transistors (second pair activated) to provide positive feedback. By activating/deactivating the second pair of load transistors, the gain of the differential amplifier is coarsely switched between a high gain mode a low gain mode, while a fine adjustment of the gain can be obtained by altering.
Abstract translation: 本申请公开了一种具有可选增益的差分放大器。 差分放大器包括一对输入晶体管，第一对负载晶体管和第二对负载晶体管。 第一对负载晶体管的漏极 - 源极路径连接在参考电位和一对输入晶体管的两个输出端之间，而栅极共同连接到控制电压。 第二对负载晶体管的漏极 - 源极路径并联连接到第一对负载晶体管的漏 - 源 - 路径。 通过控制电路，第二对负载晶体管的栅极或者连接到参考电位（第二对被去激活）或交叉耦合到该对输入晶体管的输出端（第二对被激活），以提供正反馈。 通过激活/去激活第二对负载晶体管，差分放大器的增益在高增益模式低增益模式之间粗略切换，而通过改变可以获得增益的微调。
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公开(公告)号：DE112019002561T5
公开(公告)日：2021-02-25
申请号：DE112019002561
申请日：2019-06-28
Applicant: INTEL CORP
Inventor： VENKATRAM HARIPRASATH , MOSTOFA MOHAMMED , INTI RAJESH , CHENG ROGER K , MARTIN AARON , MOZAK CHRISTOPHER , KAPPANGANTULA PAVAN KUMAR , YANG HSIEN-PAO , MANSURI MOZHGAN , JAUSSI JAMES , SRIDHARAN HARISHANKAR
IPC: G11C7/10
Abstract: Es wird eine Vorrichtung bereitgestellt, die Folgendes umfasst: eine erste Strom-versorgungsschiene zum Bereitstellen einer ersten Stromversorgung; eine zweite und eine dritte Stromversorgungsschiene zum Bereitstellen einer zweiten bzw. dritten Strom-versorgung, wobei ein Spannungspegel der ersten Stromversorgung höher ist als ein Spannungspegel sowohl der zweiten als auch der dritten Stromversorgung; eine erste Treiberschaltung, die mit der ersten Stromversorgungsschiene und mit der zweiten Strom-versorgungsschiene gekoppelt ist; eine zweite Treiberschaltung, die mit der dritten Strom-versorgungsschiene gekoppelt ist und mit der ersten Treiberschaltung gekoppelt ist; und einen Stapel von Transistoren von dem n-Leitfähigkeitstyp, der mit der ersten Strom-versorgungsschiene und mit der zweiten Treiberschaltung gekoppelt ist.
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公开(公告)号：GB2509855A
公开(公告)日：2014-07-16
申请号：GB201406362
申请日：2011-10-28
Applicant: INTEL CORP
Inventor： MOONEY STEPHEN R , HECK HOWARD , JAUSSI JAMES , CASPER BRYAN
Abstract: Systems and methods of interconnecting devices may include an input/output (IO) interface having one or more clock circuits, a power supply coupled to the one or more clock circuits, and logic to receive a rate adjustment command at the IO interface. The logic may also be configured to adjust a data rate of the IO interface in response to the rate adjustment command, and to adjust an output voltage of the power supply in response to the rate adjustment command.
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公开(公告)号：AT452465T
公开(公告)日：2010-01-15
申请号：AT04760206
申请日：2004-03-24
Applicant: INTEL CORP
Inventor： JAUSSI JAMES
Abstract: An amplifier includes multiple gain ranges. The gain range can be set by electrically adding or removing load devices.
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Patent Agency Ranking
公开(公告)号：GB2433805B
公开(公告)日：2008-07-16
申请号：GB0625616
申请日：2006-12-27
Applicant: INTEL CORP
Inventor： O'MAHONY FRANK , CASPER BRYAN , JAUSSI JAMES , HAYCOCK MATTHEW , KENNEDY JOSEPH , MANSURI MOZHAGAN , MOONEY STEPHEN R
IPC: G06F13/40
Abstract: For one disclosed embodiment, an integrated circuit may comprise an internal transmission line in one or more layers of the integrated circuit. The internal transmission line may be coupled to receive a signal from an external transmission line at a first end of the internal transmission line without use of termination circuitry. The internal transmission line may transmit the signal passively to a second end of the internal transmission line. The integrated circuit may also comprise first circuitry having an input coupled to the internal transmission line at a first location of the internal transmission line to receive the signal and second circuitry having an input coupled to the internal transmission line at a second location of the internal transmission line to receive the signal. The second location may be different from the first location. Other embodiments are also disclosed.
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公开(公告)号：DE102006061878A1
公开(公告)日：2007-08-30
申请号：DE102006061878
申请日：2006-12-28
Applicant: INTEL CORP
Inventor： O'MAHONY FRANK , CASPER BRYAN , JAUSSI JAMES , HAYCOCK MATTHEW , KENNEDY JOSEPH , MANSURI MOZHAGAN , MOONEY STEPHEN
IPC: H04L25/02
Abstract: For one disclosed embodiment, an integrated circuit may comprise an internal transmission line in one or more layers of the integrated circuit. The internal transmission line may be coupled to receive a signal from an external transmission line at a first end of the internal transmission line without use of termination circuitry. The internal transmission line may transmit the signal passively to a second end of the internal transmission line. The integrated circuit may also comprise first circuitry having an input coupled to the internal transmission line at a first location of the internal transmission line to receive the signal and second circuitry having an input coupled to the internal transmission line at a second location of the internal transmission line to receive the signal. The second location may be different from the first location. Other embodiments are also disclosed.
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公开(公告)号：EP3191969A4
公开(公告)日：2018-04-18
申请号：EP14901804
申请日：2014-12-24
Applicant: INTEL CORP
Inventor： PETHE AKSHAY , WAGH MAHESH , HARRIMAN DAVID , LIM SU WEI , DAS SHARMA DEBENDRA , FROELICH DANIEL , IYER VENKATRAMAN , JAUSSI JAMES , WU ZUOGUO
CPC classification number: G06F13/4286 , G06F13/385 , G06F13/4027 , G06F2213/0042 , G06F2213/4002
Abstract: Techniques for embedded high speed serial interface methods are described herein. The techniques include an apparatus for sideband signaling including a first serial sideband link module and a second serial sideband link module. The first serial sideband link module is to propagate packets from an upstream port to a downstream port via a first signaling lane, and the second serial sideband link module is to propagate packets from the downstream port to the upstream port via a second signaling lane.
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9.发明专利
公开(公告)号：MY175303A
公开(公告)日：2020-06-18
申请号：MYPI2014702585
申请日：2014-09-11
Applicant: INTEL CORP
Inventor： PETHE AKSHAY , WAGH MAHESH , HARRIMAN DAVID , LIM SU WEI , DAS SHARMA DEBENDRA , FROELICH DANIEL , IYER VENKATRAMAN , JAUSSI JAMES , WU ZUOGUO
Abstract: Techniques for embedded high speed serial interface methods are described herein. The techniques include an apparatus for sideband signaling including a first serial sideband link module (110) and a second serial sideband link module (112). The first serial sideband link module (110) is to propagate packets from an upstream port (102) to a downstream port (104) via a first signaling lane (114), and the second serial sideband link module (112) is to propagate packets from the downstream port (104) to the upstream port (102) via a second signaling lane (116).
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公开(公告)号：DE602004024667D1
公开(公告)日：2010-01-28
申请号：DE602004024667
申请日：2004-03-24
Applicant: INTEL CORP
Inventor： JAUSSI JAMES
Abstract: An amplifier includes multiple gain ranges. The gain range can be set by electrically adding or removing load devices.
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