公开(公告)号：WO2007050882A2

公开(公告)日：2007-05-03

申请号：PCT/US2006041991

申请日：2006-10-26

Applicant: INTEL CORP ,  MOHANAVELU RAVINDRAN ,  MARTIN AARON ,  KESLING DAWSON ,  SALMON JOE ,  UR RASHID MAMUN

Inventor： MOHANAVELU RAVINDRAN ,  MARTIN AARON ,  KESLING DAWSON ,  SALMON JOE ,  UR RASHID MAMUN

IPC: G06F1/10

CPC classification number: G06F1/04 ,  G06F1/10

Abstract: Embodiments of the invention are generally directed to systems, methods, and apparatuses for a clocking architecture using a bidirectional clock. In an embodiment, a chip includes a bidirectional clock port capable of being statically configured to receive or to transmit a reference clock. In one embodiment, the chip includes a first port to receive data and a second port, wherein the chip repeats at least a portion of the data that it receives on the first port to a transmitter at the second port. Other embodiments are described and claimed.

Abstract translation: 本发明的实施例通常涉及用于使用双向时钟的时钟架构的系统，方法和设备。 在一个实施例中，芯片包括能够被静态配置为接收或发送参考时钟的双向时钟端口。 在一个实施例中，芯片包括用于接收数据的第一端口和第二端口，其中芯片重复在第一端口上向第二端口处的发射器接收的数据的至少一部分。 描述并要求保护其他实施例。

公开(公告)号：DE112006002559T5

公开(公告)日：2008-08-28

申请号：DE112006002559

申请日：2006-10-26

Applicant: INTEL CORP

Inventor： MOHANAVELU RAVINDRAN ,  MARTIN AARON ,  KESLING DAWSON ,  SALMON JOE ,  RASHID MAMUN UR

IPC: G06F1/10

Abstract: Embodiments of the invention are generally directed to systems, methods, and apparatuses for a clocking architecture using a bidirectional clock. In an embodiment, a chip includes a bidirectional clock port capable of being statically configured to receive or to transmit a reference clock. In one embodiment, the chip includes a first port to receive data and a second port, wherein the chip repeats at least a portion of the data that it receives on the first port to a transmitter at the second port. Other embodiments are described and claimed.

公开(公告)号：DE112011105701T5

公开(公告)日：2014-07-17

申请号：DE112011105701

申请日：2011-10-01

Applicant: INTEL CORP

Inventor： FALCONER MAYNARD C ,  TERY KEVIN P ,  SKINNER HARRY G ,  KESLING DAWSON

IPC: H03M7/00 ,  H04B15/00 ,  H04L27/34

Abstract: Ein Verfahren zum Verwalten von Informationen weist Empfangen von Datenbit, Bestimmen von Zeigern für Bit bei nur einer Frequenz eines Übertragungsspektrums, Kombinieren der Zeiger von Bit, die einen Zeiger bilden, der eine Spektralenergie aufweist, die in einem vorbestimmten Bereich liegt, und Bilden eines Codeworts aus den Bit der kombinierten Zeiger auf.

公开(公告)号：DE112006002559B4

公开(公告)日：2010-04-29

申请号：DE112006002559

申请日：2006-10-26

Applicant: INTEL CORP

Inventor： MOHANAVELU RAVINDRAN ,  MARTIN AARON ,  KESLING DAWSON ,  SALMON JOE ,  RASHID MAMUN UR

IPC: G06F1/10

Abstract: Embodiments of the invention are generally directed to systems, methods, and apparatuses for a clocking architecture using a bidirectional clock. In an embodiment, a chip includes a bidirectional clock port capable of being statically configured to receive or to transmit a reference clock. In one embodiment, the chip includes a first port to receive data and a second port, wherein the chip repeats at least a portion of the data that it receives on the first port to a transmitter at the second port. Other embodiments are described and claimed.

公开(公告)号：GB2445698B

公开(公告)日：2010-11-03

申请号：GB0807407

申请日：2006-10-26

Applicant: INTEL CORP

Inventor： MOHANAVELU RAVINDRAN ,  MARTIN AARON ,  KESLING DAWSON ,  SALMON JOE ,  RASHID MAMUN UR

IPC: G06F1/04 ,  G06F1/10

Abstract: Embodiments of the invention are generally directed to systems, methods, and apparatuses for a clocking architecture using a bidirectional clock. In an embodiment, a chip includes a bidirectional clock port capable of being statically configured to receive or to transmit a reference clock. In one embodiment, the chip includes a first port to receive data and a second port, wherein the chip repeats at least a portion of the data that it receives on the first port to a transmitter at the second port. Other embodiments are described and claimed.

公开(公告)号：GB2445698A

公开(公告)日：2008-07-16

申请号：GB0807407

申请日：2006-10-26

Applicant: INTEL CORP

Inventor： MOHANAVELU RAVINDRAN ,  MARTIN AARON ,  KESLING DAWSON ,  SALMON JOE ,  RASHID MAMUN UR

IPC: G06F1/04 ,  H03K19/0175

Abstract: Embodiments of the invention are generally directed to systems, methods, and apparatuses for a clocking architecture using a bidirectional clock. In an embodiment, a chip includes a bidirectional clock port capable of being statically configured to receive or to transmit a reference clock. In one embodiment, the chip includes a first port to receive data and a second port, wherein the chip repeats at least a portion of the data that it receives on the first port to a transmitter at the second port. Other embodiments are described and claimed.