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    2.
    发明专利
    未知

    公开(公告)号：DE112006002559T5

    公开(公告)日：2008-08-28

    申请号：DE112006002559

    申请日：2006-10-26

    Applicant: INTEL CORP

    Inventor： MOHANAVELU RAVINDRAN ,  MARTIN AARON ,  KESLING DAWSON ,  SALMON JOE ,  RASHID MAMUN UR

    IPC: G06F1/10

    Abstract: Embodiments of the invention are generally directed to systems, methods, and apparatuses for a clocking architecture using a bidirectional clock. In an embodiment, a chip includes a bidirectional clock port capable of being statically configured to receive or to transmit a reference clock. In one embodiment, the chip includes a first port to receive data and a second port, wherein the chip repeats at least a portion of the data that it receives on the first port to a transmitter at the second port. Other embodiments are described and claimed.

    Verfahren, Vorrichtung und System zum zeitlichen entzerren des Empfangstaktes
    3.
    发明专利
    Verfahren, Vorrichtung und System zum zeitlichen entzerren des Empfangstaktes 未知

    公开(公告)号：DE112006003551B4

    公开(公告)日：2013-04-18

    申请号：DE112006003551

    申请日：2006-12-11

    Applicant: INTEL CORP

    Inventor： LAW HON-MO RAYMOND ,  RASHID MAMUN UR ,  MARTIN AARON K

    IPC: H04L7/033 ,  H03L7/081

    Abstract: Integrierte Schaltung, umfassend: eine Takteingabeanschlußstelle (202) zum Empfangen eines Eingangstaktsignals (CKIN); eine Dateneingabeanschlußstelle (252) zum Empfangen eines Datensignals (DIN); einen Taktgenerator (220), der zum Empfangen des Eingangstaktsignals (CKIN) angeschlossen ist; mehrere Phaseninterpolatoren (224, 226, 228), die auf den Taktgenerator (220) reagieren, um mehrere lokale Taktsignale zu erzeugen, wobei mindestens eines der mehreren lokalen Taktsignale eine Phase hat, die sich zum Takten des Datensignals (DIN) eignet; einen Phasendetektor (232), der zum Vergleichen des Eingangstaktsignals (CKIN) und eines der mehreren lokalen Taktsignale angekoppelt ist; und Phaseninterpolatorsteuerlogik (210) zur Beeinflussung des Betriebs der mehreren Phaseninterpolatoren (224, 226, 228), die auf ein Signal vom Phasendetektor (232) reagieren, wobei die mehreren Phaseninterpolatoren (224, 226, 228) umfassen: einen ersten Phaseninterpolator (226) zum Erzeugen eines ersten lokalen Taktsignals; einen zweiten Phaseninterpolator (228) zum Erzeugen eines zweiten lokalen Taktsignals, das für den Phasendetektor (232) bereitgestellt ist, wobei die integrierte...

    4.
    发明专利
    未知

    公开(公告)号：DE112006002559B4

    公开(公告)日：2010-04-29

    申请号：DE112006002559

    申请日：2006-10-26

    Applicant: INTEL CORP

    Inventor： MOHANAVELU RAVINDRAN ,  MARTIN AARON ,  KESLING DAWSON ,  SALMON JOE ,  RASHID MAMUN UR

    IPC: G06F1/10

    Abstract: Embodiments of the invention are generally directed to systems, methods, and apparatuses for a clocking architecture using a bidirectional clock. In an embodiment, a chip includes a bidirectional clock port capable of being statically configured to receive or to transmit a reference clock. In one embodiment, the chip includes a first port to receive data and a second port, wherein the chip repeats at least a portion of the data that it receives on the first port to a transmitter at the second port. Other embodiments are described and claimed.

    5.
    发明专利
    未知

    公开(公告)号：DE112004002521T5

    公开(公告)日：2006-11-09

    申请号：DE112004002521

    申请日：2004-12-22

    Applicant: INTEL CORP

    Inventor： RASHID MAMUN UR

    IPC: H03L7/099 ,  H03K5/00 ,  H03K5/13 ,  H03K5/135 ,  H03L7/081

    Abstract: Embodiments of the invention provide for a delay locked loop architecture including a coarse-fine type arrangement using one loop for non-continuous strobe that can be also be configured for continuous clocks as well. In particular, a reference loop establishes precise coarse unit delay. A slave delay line duplicates unit delay. A phase interpolator interpolates between unit delay to produce fine delay.

    A clocking architecture using a bi-directional reference clock
    7.
    发明专利
    A clocking architecture using a bi-directional reference clock 未知

    公开(公告)号：GB2445698B

    公开(公告)日：2010-11-03

    申请号：GB0807407

    申请日：2006-10-26

    Applicant: INTEL CORP

    Inventor： MOHANAVELU RAVINDRAN ,  MARTIN AARON ,  KESLING DAWSON ,  SALMON JOE ,  RASHID MAMUN UR

    IPC: G06F1/04 ,  G06F1/10

    Abstract: Embodiments of the invention are generally directed to systems, methods, and apparatuses for a clocking architecture using a bidirectional clock. In an embodiment, a chip includes a bidirectional clock port capable of being statically configured to receive or to transmit a reference clock. In one embodiment, the chip includes a first port to receive data and a second port, wherein the chip repeats at least a portion of the data that it receives on the first port to a transmitter at the second port. Other embodiments are described and claimed.

    A clocking architecture using a bi-directional reference clock
    8.
    发明专利
    A clocking architecture using a bi-directional reference clock 未知

    公开(公告)号：GB2445698A

    公开(公告)日：2008-07-16

    申请号：GB0807407

    申请日：2006-10-26

    Applicant: INTEL CORP

    Inventor： MOHANAVELU RAVINDRAN ,  MARTIN AARON ,  KESLING DAWSON ,  SALMON JOE ,  RASHID MAMUN UR

    IPC: G06F1/04 ,  H03K19/0175

    Abstract: Embodiments of the invention are generally directed to systems, methods, and apparatuses for a clocking architecture using a bidirectional clock. In an embodiment, a chip includes a bidirectional clock port capable of being statically configured to receive or to transmit a reference clock. In one embodiment, the chip includes a first port to receive data and a second port, wherein the chip repeats at least a portion of the data that it receives on the first port to a transmitter at the second port. Other embodiments are described and claimed.

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