公开(公告)号：MY188298A

公开(公告)日：2021-11-25

申请号：MYPI2017700394

申请日：2014-09-09

Applicant: INTEL CORP

Inventor： JUN KIMIN ,  DASGUPTA SANSAPTAK ,  LEVANDER ALEJANDRO X ,  MORROW PATRICK

IPC: H01L29/778 ,  H01L21/337 ,  H01L21/338 ,  H01L29/808 ,  H01L29/812

Abstract: A multi-gate high electron mobility transistor, HEMT, and its methods of formation are disclosed. The multi-gate HEMT includes a substrate (102) and an adhesion layer (104) on top of the substrate (102). A channel layer (120) is disposed on top of the adhesion layer (104), and a first gate electrode (106) is disposed on top of the channel layer (120). The first gate electrode (106) has a first gate dielectric layer (116) in between the first gate electrode (106) and the channel layer (120). A second gate electrode (108) is embedded within the substrate (102) and beneath the channel layer (120). The second gate electrode (108) has a second gate dielectric layer (118) completely surrounding the second gate electrode (108). A pair of source and drain contacts (110) are disposed on opposite sides of the first gate electrode (106). (Figure 1B)

公开(公告)号：EP3155665A4

公开(公告)日：2018-02-21

申请号：EP14894669

申请日：2014-06-13

Applicant: INTEL CORP

Inventor： JUN KIMIN ,  DASGUPTA SANSAPTAK ,  LEVANDER ALEJANDRO X ,  MORROW PATRICK

IPC: H01L29/778 ,  H01L21/336 ,  H01L29/04 ,  H01L29/20

CPC classification number: H01L29/7787 ,  H01L21/0254 ,  H01L21/02609 ,  H01L21/76254 ,  H01L21/7806 ,  H01L29/045 ,  H01L29/2003 ,  H01L29/205 ,  H01L29/66462 ,  H01L29/7781

Abstract: A method including forming a barrier layer on a polar compound semiconductor layer on a sacrificial substrate; coupling the sacrificial substrate to a carrier substrate to form a composite structure wherein the barrier layer is disposed between the polar compound semiconductor layer and the carrier substrate; separating the sacrificial substrate from the composite structure to expose the polar compound semiconductor layer; and forming at least one circuit device. An apparatus including a barrier layer on a substrate; a transistor device on the barrier layer; and a polar compound semiconductor layer disposed between the barrier layer and the transistor device, the polar compound semiconductor layer including a two-dimensional electron gas therein.

公开(公告)号：EP3087583A4

公开(公告)日：2017-08-09

申请号：EP14873496

申请日：2014-11-19

Applicant: INTEL CORP

Inventor： LEVANDER ALEJANDRO X ,  JUN KIMIN

IPC: H01L21/20

CPC classification number: H01L27/1207 ,  H01L21/02002 ,  H01L21/02521 ,  H01L21/02634 ,  H01L21/02642 ,  H01L21/02647 ,  H01L21/265 ,  H01L21/31053 ,  H01L21/31111 ,  H01L21/76251 ,  H01L21/76254 ,  H01L27/1203 ,  H01L29/0649 ,  H01L29/26

Abstract: Techniques are disclosed for heteroepitaxial growth of a layer of lattice-mismatched semiconductor material on an initial substrate, and transfer of a defect-free portion of that layer to a handle wafer or other suitable substrate for integration. In accordance with some embodiments, transfer may result in the presence of island-like oxide structures on the handle wafer/substrate, each having a defect-free island of the lattice-mismatched semiconductor material embedded within its upper surface. Each defect-free semiconductor island may have one or more crystalline faceted edges and, with its accompanying oxide structure, may provide a planar surface for integration. In some cases, a layer of a second, different semiconductor material may be heteroepitaxially grown over the handle wafer/substrate to fill areas around the transferred islands. In some other cases, the handle wafer/substrate itself may be homoepitaxially grown to fill areas around the transferred islands.

Abstract translation: 公开了用于初始衬底上的晶格失配半导体材料层的异质外延生长以及将该层的无缺陷部分转移至处理晶片或其他合适衬底以进行集成的技术。 根据一些实施例，转移可导致处理晶片/衬底上存在岛状氧化物结构，每个具有嵌入其上表面内的晶格失配半导体材料的无缺陷岛。 每个无缺陷半导体岛可以具有一个或多个晶体有小面的边缘，并且与其伴随的氧化物结构一起可以提供用于集成的平坦表面。 在一些情况下，可以在处理晶片/衬底上异质外延生长一层第二不同半导体材料以填充转移岛周围的区域。 在一些其他情况下，处理晶片/衬底本身可以同质生长以填充转移岛周围的区域。

公开(公告)号：EP3192101A4

公开(公告)日：2018-05-23

申请号：EP14901471

申请日：2014-09-09

Applicant: INTEL CORP

Inventor： JUN KIMIN ,  DASGUPTA SANSAPTAK ,  LEVANDER ALEJANDRO X ,  MORROW PATRICK

IPC: H01L29/778 ,  H01L21/336 ,  H01L21/762 ,  H01L29/20 ,  H01L29/423

CPC classification number: H01L29/7781 ,  H01L21/76254 ,  H01L29/2003 ,  H01L29/42356 ,  H01L29/42376 ,  H01L29/66462 ,  H01L29/66545

Abstract: A multi-gate high electron mobility transistor (HEMT) and its methods of formation are disclosed. The multi-gate HEMT includes a substrate and an adhesion layer on top of the substrate. A channel layer is disposed on top of the adhesion layer, and a first gate electrode is disposed on top of the channel layer. The first gate electrode has a first gate dielectric layer in between the first gate electrode and the channel layer. A second gate electrode is embedded within the substrate and beneath the channel layer. The second gate electrode has a second gate dielectric layer completely surrounding the second gate electrode. A pair of source and drain contacts are disposed on opposite sides of the first gate electrode.