公开(公告)号：WO2013095529A9

公开(公告)日：2013-10-17

申请号：PCT/US2011066941

申请日：2011-12-22

Applicant: INTEL CORP ,  GOPAL VINODH ,  GUILFORD JAMES D ,  WOLRICH GILBERT M ,  FEGHALI WAJDI K ,  OZTURK ERDINC ,  DIXON MARTIN G ,  MIRKES SEAN P ,  MERTEN MATTHEW C ,  LI TONG ,  TOLL BRET L

Inventor： GOPAL VINODH ,  GUILFORD JAMES D ,  WOLRICH GILBERT M ,  FEGHALI WAJDI K ,  OZTURK ERDINC ,  DIXON MARTIN G ,  MIRKES SEAN P ,  MERTEN MATTHEW C ,  LI TONG ,  TOLL BRET L

IPC: G06F9/30 ,  G06F9/305 ,  G06F13/14

CPC classification number: G06F9/3001 ,  G06F9/30094 ,  G06F9/3838

Abstract: A number of addition instructions are provided that have no data dependency between each other. A first addition instruction stores its carry output in a first flag of a flags register without modifying a second flag in the flags register. A second addition instruction stores its carry output in the second flag of the flags register without modifying the first flag in the flags register.

Abstract translation: 提供了彼此之间没有数据依赖性的多个附加指令。 第一加法指令将其进位输出存储在标志寄存器的第一标志中，而不修改标志寄存器中的第二标志。 第二加法指令将其进位输出存储在标志寄存器的第二标志中，而不修改标志寄存器中的第一个标志。

公开(公告)号：EP3014452A4

公开(公告)日：2017-04-26

申请号：EP13887960

申请日：2013-06-27

Applicant: INTEL CORP

Inventor： SCHMITT THILO ,  LACHNER PETER ,  STRONG BEEMAN ,  LEVY OFER ,  TOLL THOMAS ,  MERTEN MATTHEW ,  LI TONG ,  RAJWAR RAVI ,  LAI KONRAD

IPC: G06F11/36 ,  G06F9/30

CPC classification number: G06F9/30189 ,  G06F11/3636

Abstract: In accordance with embodiments disclosed herein, there is provided systems and methods for tracking the mode of processing devices in an instruction tracing system. The method may include receiving an indication of a change in a current execution mode of the processing device. The method may also include determining that the current execution mode of the received indication is different than a value of an execution mode of a first execution mode (EM) packet previously-generated by the IT module. The method may also include generating, based on the determining that the current execution mode is different, a second EM packet that provides a value of the current execution mode of the processing device to indicate the change in the execution mode for an instruction in a trace generated by the IT module. The method may further include generating transactional memory (TMX) packets having n bit mode pattern in the packet log. The n is at least two and the n bit mode indicates transaction status of the TMX operation.

Abstract translation: 根据这里公开的实施例，提供了用于跟踪指令跟踪系统中处理设备的模式的系统和方法。 该方法可以包括接收处理设备的当前执行模式的改变的指示。 该方法还可以包括确定接收到的指示的当前执行模式不同于由IT模块先前生成的第一执行模式（EM）分组的执行模式的值。 该方法还可以包括基于确定当前执行模式是不同的第二EM分组来提供处理设备的当前执行模式的值以指示执行模式中的轨迹中的指令的改变 由IT模块生成。 该方法还可以包括在分组日志中生成具有n位模式模式的事务存储器（TMX）分组。 n至少为2，n位模式表示TMX操作的事务状态。

公开(公告)号：EP2984557A4

公开(公告)日：2017-12-20

申请号：EP14782269

申请日：2014-04-09

Applicant: INTEL CORP

Inventor： KADGI VIJAYKUMAR B ,  ANDERSON JEREMY R ,  HADLEY JAMES D ,  LI TONG ,  MERTEN MATTHEW C

IPC: G06F9/30 ,  G06F9/38

CPC classification number: G06F9/30105 ,  G06F8/443 ,  G06F9/30032 ,  G06F9/30094 ,  G06F9/30098 ,  G06F9/3013 ,  G06F9/30181 ,  G06F9/3838 ,  G06F9/384 ,  G06F9/3857

Abstract: Systems and methods for flag tracking in data manipulation operations involving move elimination. An example processing system comprises a first data structure including a plurality of physical register values; a second data structure including a plurality of pointers referencing elements of the first data structure; a third data structure including a plurality of move elimination sets, each move elimination set comprising two or more bits representing two or more logical data registers, the third data structure further comprising at least one bit associated with each move elimination set, the at least one bit representing one or more logical flag registers; a fourth data structure including an identifier of a data register sharing an element of the first data structure with a flag register; and a move elimination logic configured to perform a move elimination operation.