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    Compare and exchange operation using sleep-wakeup mechanism
    2.
    发明专利
    Compare and exchange operation using sleep-wakeup mechanism 有权
    使用睡眠唤醒机制的比较和交换操作

    公开(公告)号：JP2009151793A

    公开(公告)日：2009-07-09

    申请号：JP2008324669

    申请日：2008-12-19

    Applicant: Intel Corp ,  インテル・コーポレーション

    Inventor： SAHA BRATIN ,  MERTEN MATTHEW ,  HAMMARLUND PER

    IPC: G06F9/52 ,  G06F12/00

    CPC classification number: G06F9/30021 ,  G06F9/30032 ,  G06F9/3004 ,  G06F9/30087 ,  G06F9/3857 ,  G06F9/526 ,  G06F2209/521

    Abstract: PROBLEM TO BE SOLVED: To provide a method, device and system for performing comparison and exchange operation by using one sleep-wakeup mechanism.
    SOLUTION: According to one embodiment, one instruction in one process is executed to help acquire a lock on behalf of the processor. When the lock is unavailable to be acquired by the processor, the instruction is put to sleep until one event occurs. While the instruction is put to sleep, the memory system of the processor monitors the change of the lock value. When the lock value is tired to be changed, or the value is changed, the wakeup of the instruction put to sleep is triggered.
    COPYRIGHT: (C)2009,JPO&INPIT

    Abstract translation: 要解决的问题：提供一种通过使用一个睡眠唤醒机制进行比较和交换操作的方法，装置和系统。 解决方案：根据一个实施例，一个进程中的一个指令被执行以帮助代表处理器获取锁定。 当锁不能由处理器获取时，指令进入休眠状态直到发生一个事件。 当指令进入休眠状态时，处理器的内存系统会监视锁定值的变化。 当锁定值被改变，或者值改变时，触发唤醒指令进入睡眠状态。 版权所有（C）2009，JPO＆INPIT

    Compare and exchange operation using sleep-wakeup mechanism
    3.
    发明专利
    Compare and exchange operation using sleep-wakeup mechanism 审中-公开
    使用睡眠唤醒机制的比较和交换操作

    公开(公告)号：JP2006031691A

    公开(公告)日：2006-02-02

    申请号：JP2005178287

    申请日：2005-06-17

    Applicant: Intel Corp ,  インテル・コーポレーション

    Inventor： SAHA BRATIN ,  MERTEN MATTHEW ,  HAMMARLUND PER

    IPC: G06F9/52 ,  G06F1/32 ,  G06F9/38 ,  G06F9/46 ,  G06F12/00

    CPC classification number: G06F9/30021 ,  G06F9/30032 ,  G06F9/3004 ,  G06F9/30087 ,  G06F9/3857 ,  G06F9/526 ,  G06F2209/521

    Abstract: PROBLEM TO BE SOLVED: To improve bottlenecking of resources, waste of memory bandwidth, compute bandwidth, microarchitectural resources and power which are generated when waiting for lock of a share resource between processors (or threads) to become available.
    SOLUTION: A method, apparatus and system are provided for performing compare and exchange operations using a sleep-wakeup mechanism. According to one embodiment, an instruction at a processor is executed to help acquire a lock on behalf of the processor. If the lock is unavailable to be acquired by the processor, the instruction is put to sleep until an event has occurred.
    COPYRIGHT: (C)2006,JPO&NCIPI

    Abstract translation: 要解决的问题：为了改善资源的瓶颈，浪费存储器带宽，计算带宽，微架构资源和在等待处理器（或线程）之间的共享资源锁定可用时生成的功率。 解决方案：提供了一种使用睡眠唤醒机制进行比较和交换操作的方法，装置和系统。 根据一个实施例，执行处理器处的指令以帮助代表处理器获取锁定。 如果锁不能由处理器获取，则指令将进入休眠状态，直到发生事件为止。 版权所有（C）2006，JPO＆NCIPI

    TRACKING MODE OF A PROCESSING DEVICE IN INSTRUCTION TRACING SYSTEMS
    6.
    发明公开
    TRACKING MODE OF A PROCESSING DEVICE IN INSTRUCTION TRACING SYSTEMS 审中-公开
    VERFOLGUNGSMODUS EINER VERARBEITUNGSVORRICHTUNG IN BEFHHLSVERFOLGUNGSSYSTEMEN

    公开(公告)号：EP3014452A4

    公开(公告)日：2017-04-26

    申请号：EP13887960

    申请日：2013-06-27

    Applicant: INTEL CORP

    Inventor： SCHMITT THILO ,  LACHNER PETER ,  STRONG BEEMAN ,  LEVY OFER ,  TOLL THOMAS ,  MERTEN MATTHEW ,  LI TONG ,  RAJWAR RAVI ,  LAI KONRAD

    IPC: G06F11/36 ,  G06F9/30

    CPC classification number: G06F9/30189 ,  G06F11/3636

    Abstract: In accordance with embodiments disclosed herein, there is provided systems and methods for tracking the mode of processing devices in an instruction tracing system. The method may include receiving an indication of a change in a current execution mode of the processing device. The method may also include determining that the current execution mode of the received indication is different than a value of an execution mode of a first execution mode (EM) packet previously-generated by the IT module. The method may also include generating, based on the determining that the current execution mode is different, a second EM packet that provides a value of the current execution mode of the processing device to indicate the change in the execution mode for an instruction in a trace generated by the IT module. The method may further include generating transactional memory (TMX) packets having n bit mode pattern in the packet log. The n is at least two and the n bit mode indicates transaction status of the TMX operation.

    Abstract translation: 根据这里公开的实施例，提供了用于跟踪指令跟踪系统中处理设备的模式的系统和方法。 该方法可以包括接收处理设备的当前执行模式的改变的指示。 该方法还可以包括确定接收到的指示的当前执行模式不同于由IT模块先前生成的第一执行模式（EM）分组的执行模式的值。 该方法还可以包括基于确定当前执行模式是不同的第二EM分组来提供处理设备的当前执行模式的值以指示执行模式中的轨迹中的指令的改变 由IT模块生成。 该方法还可以包括在分组日志中生成具有n位模式模式的事务存储器（TMX）分组。 n至少为2，n位模式表示TMX操作的事务状态。

    Techniken zur Verwendung von Speicher-Attributen
    7.
    发明专利
    Techniken zur Verwendung von Speicher-Attributen 未知

    公开(公告)号：DE102007006190B4

    公开(公告)日：2017-10-26

    申请号：DE102007006190

    申请日：2007-02-07

    Applicant: INTEL CORP

    Inventor： JACOBSON QUINN ,  BRACY ANNE ,  WANG HONG ,  SHEN JOHN ,  HAMMARLUND PER ,  MERTEN MATTHEW ,  SRINIVAS SURESH ,  DOSHI KSHITIJ ,  CHINYA GAUTHAM ,  SAHA BRATIN ,  ADL-TABATABAI ALI-REZA ,  SHEAFFER GAD

    IPC: G06F12/02 ,  G06F12/00

    Abstract: Maschinenlesbares Medium, auf dem ein Satz Befehle gespeichert ist, die, wenn sie von einer Maschine ausgeführt werden, die Maschine dazu veranlassen, ein Verfahren auszuführen, das aufweist: Lesen eines Attributbits (115), welches einer Cache-Speicherlinie (105) zugeordnet ist, wobei die Cache-Speicherlinie (105) nur einem Software-Thread in einem Multi-Thread-Programm zugeordnet ist, wobei das Attributbit (115) als ein Ergebnis des Ausführens eines Befehls geprüft wird, und wobei das Attributbit (115) durch Ausführen eines load_check Befehls gelesen wird und das Attributbit durch Ausführen eines load_set Befehls gesetzt wird; Bestimmen des Werts des Attributbits (115), wobei das Bestimmen des Werts des Attributbits (115) das Ausführen eines Architekturszenarios in einem Prozessor der Maschine aufweist, wobei das Szenario bestimmt, ob die Cache-Speicherlinie (115) sich in einem unerwarteten Zustand befindet; Ausführen eines leichtgewichtigen Yield-Ereignisses in Reaktion auf das Bestimmen des Werts des Attributbits (115).

    Computer memory attributes
    10.
    发明专利
    Computer memory attributes 未知

    公开(公告)号：GB2434892A

    公开(公告)日：2007-08-08

    申请号：GB0702377

    申请日：2007-02-07

    Applicant: INTEL CORP

    Inventor： JACOBSON QUINN A ,  BRACY ANNE ,  WANG HONG ,  SHEN JOHN ,  HAMMARLUND PER ,  MERTEN MATTHEW ,  SRINIVAS SURESH ,  DOSHI KSHITIJ ,  CHINYA GAUTHAM ,  SAHA BRATIN ,  ADL-TABATABAI ALI-REZA ,  SHEAFFER GAD S

    IPC: G06F12/14 ,  G06F12/08

    Abstract: A memory block in a computer has attributes associated with it. The attributes may correspond to a single software thread. The memory may be associated with a cache line 105 in a cache 100 and the attributes may be stored as flags 115 in the cache. The attributes may indicate the thread to which the cache line corresponds. The processor may be able to check or set the attributes when loading the line from the cache. The processor may generate a light weight yield event or invoke a handler in response to the values of the attributes. The processor may have several cores and the cache may be in the processor. The attributes may indicate that the cache line has been marked for analysis by a tool such as a performance monitoring tool or a debugging tool. The attributes may be set by an instrumentation tool.

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