公开(公告)号：JP2011175669A

公开(公告)日：2011-09-08

申请号：JP2011102812

申请日：2011-05-02

Applicant: Intel Corp ,  インテル コーポレイション

Inventor： SAHA BRATIN ,  MERTEN MATTHEW C ,  HAMMARLUND PER

IPC: G06F9/38 ,  G06F9/52 ,  G06F12/08

CPC classification number: G06F9/3004 ,  G06F9/30087 ,  G06F9/3834 ,  G06F9/3842

Abstract: PROBLEM TO BE SOLVED: To provide a method and apparatus for executing lock instructions speculatively in an out-of-order processor.
SOLUTION: In one embodiment, a prediction is made whether a given lock instruction will actually be contended. If not, then the lock instruction may be treated as having a normal load micro-operation which may be speculatively executed. Monitor logic may look for indications that the lock instruction is actually contended. If no such indications are found, the speculative load micro-operation and other micro-operations corresponding to the lock instruction may retire. However, if such indications are in fact found, the lock instruction may be restarted, and the prediction mechanism may be updated.
COPYRIGHT: (C)2011,JPO&INPIT

Abstract translation: 要解决的问题：提供一种用于在乱序处理器中推测地执行锁定指令的方法和装置。 解决方案：在一个实施例中，预测给定的锁定指令是否将被实际地竞争。 如果不是，则锁定指令可以被视为具有可以推测地执行的正常负载微操作。 监视器逻辑可能会查找锁定指令实际上有争议的迹象。 如果没有发现这样的指示，则与锁定指令相对应的投机负载微操作和其他微操作可能会退出。 然而，如果事实上发现这样的指示，则可以重新启动锁定指令，并且可以更新预测机制。 版权所有（C）2011，JPO＆INPIT

公开(公告)号：DE112005001515T5

公开(公告)日：2007-05-10

申请号：DE112005001515

申请日：2005-06-17

Applicant: INTEL CORP

Inventor： SAHA BRATIN ,  MERTEN MATTHEW C ,  HAMMARLUND PER

IPC: G06F9/38

Abstract: A method and apparatus for executing lock instructions speculatively in an out-of-order processor are disclosed. In one embodiment, a prediction is made whether a given lock instruction will actually be contended. If not, then the lock instruction may be treated as having a normal load micro-operation which may be speculatively executed. Monitor logic may look for indications that the lock instruction is actually contended. If no such indications are found, the speculative load micro-operation and other micro-operations corresponding to the lock instruction may retire. However, if such indications are in fact found, the lock instruction may be restarted, and the prediction mechanism may be updated.

公开(公告)号：WO2013095529A9

公开(公告)日：2013-10-17

申请号：PCT/US2011066941

申请日：2011-12-22

Applicant: INTEL CORP ,  GOPAL VINODH ,  GUILFORD JAMES D ,  WOLRICH GILBERT M ,  FEGHALI WAJDI K ,  OZTURK ERDINC ,  DIXON MARTIN G ,  MIRKES SEAN P ,  MERTEN MATTHEW C ,  LI TONG ,  TOLL BRET L

Inventor： GOPAL VINODH ,  GUILFORD JAMES D ,  WOLRICH GILBERT M ,  FEGHALI WAJDI K ,  OZTURK ERDINC ,  DIXON MARTIN G ,  MIRKES SEAN P ,  MERTEN MATTHEW C ,  LI TONG ,  TOLL BRET L

IPC: G06F9/30 ,  G06F9/305 ,  G06F13/14

CPC classification number: G06F9/3001 ,  G06F9/30094 ,  G06F9/3838

Abstract: A number of addition instructions are provided that have no data dependency between each other. A first addition instruction stores its carry output in a first flag of a flags register without modifying a second flag in the flags register. A second addition instruction stores its carry output in the second flag of the flags register without modifying the first flag in the flags register.

Abstract translation: 提供了彼此之间没有数据依赖性的多个附加指令。 第一加法指令将其进位输出存储在标志寄存器的第一标志中，而不修改标志寄存器中的第二标志。 第二加法指令将其进位输出存储在标志寄存器的第二标志中，而不修改标志寄存器中的第一个标志。

公开(公告)号：WO2006012103A2

公开(公告)日：2006-02-02

申请号：PCT/US2005021838

申请日：2005-06-17

Applicant: INTEL CORP ,  SAHA BRATIN ,  MERTEN MATTHEW C ,  HAMMARLUND PER

Inventor： SAHA BRATIN ,  MERTEN MATTHEW C ,  HAMMARLUND PER

IPC: G06F9/00

CPC classification number: G06F9/3004 ,  G06F9/30087 ,  G06F9/3834 ,  G06F9/3842

Abstract: A method and apparatus for executing lock instructions speculatively in an out-of-order processor are disclosed. In one embodiment, a prediction is made whether a given lock instruction will actually be contended. If not, then the lock instruction may be treated as having a normal load micro-operation which may be speculatively executed. Monitor logic may look for indications that the lock instruction is actually contended. If no such indications are found, the speculative load micro-operation and other micro-operations corresponding to the lock instruction may retire. However, if such indications are in fact found, the lock instruction may be restarted, and the prediction mechanism may be updated.

Abstract translation: 公开了一种在无序处理器中推测性地执行锁定指令的方法和设备。 在一个实施例中，预测给定的锁定指令是否实际上将被争用。 如果不是，则锁定指令可被视为具有可被推测执行的正常加载微操作。 监视逻辑可以查找锁指令实际上是否存在争用的指示。 如果没有找到这样的指示，则可以撤销对应于锁定指令的推测加载微操作和其他微操作。 但是，如果实际上发现了这样的指示，那么可以重新开始锁定指令，并且可以更新预测机制。

公开(公告)号：EP2984557A4

公开(公告)日：2017-12-20

申请号：EP14782269

申请日：2014-04-09

Applicant: INTEL CORP

Inventor： KADGI VIJAYKUMAR B ,  ANDERSON JEREMY R ,  HADLEY JAMES D ,  LI TONG ,  MERTEN MATTHEW C

IPC: G06F9/30 ,  G06F9/38

CPC classification number: G06F9/30105 ,  G06F8/443 ,  G06F9/30032 ,  G06F9/30094 ,  G06F9/30098 ,  G06F9/3013 ,  G06F9/30181 ,  G06F9/3838 ,  G06F9/384 ,  G06F9/3857

Abstract: Systems and methods for flag tracking in data manipulation operations involving move elimination. An example processing system comprises a first data structure including a plurality of physical register values; a second data structure including a plurality of pointers referencing elements of the first data structure; a third data structure including a plurality of move elimination sets, each move elimination set comprising two or more bits representing two or more logical data registers, the third data structure further comprising at least one bit associated with each move elimination set, the at least one bit representing one or more logical flag registers; a fourth data structure including an identifier of a data register sharing an element of the first data structure with a flag register; and a move elimination logic configured to perform a move elimination operation.

公开(公告)号：EP2831749A4

公开(公告)日：2016-01-06

申请号：EP12873063

申请日：2012-03-30

Applicant: INTEL CORP

Inventor： CAPRIOLI PAUL ,  MERTEN MATTHEW C ,  AL-OTOOM MUAWYA M ,  SHAIKH OMAR M ,  KANHERE ABHAY S ,  SRINIVAS SURESH ,  YAMADA KOICHI ,  THAKKAR VIVEK ,  OSCIAK PAWEL

IPC: G06F15/80 ,  G06F9/30 ,  G06F9/38 ,  G06F13/14

CPC classification number: G06F11/3466 ,  G06F8/40 ,  G06F8/52 ,  G06F9/3017 ,  G06F9/3842 ,  G06F9/4552 ,  G06F11/073 ,  G06F11/3616 ,  G06F11/3652

Abstract: A hardware profiling mechanism implemented by performance monitoring hardware enables page level automatic binary translation. The hardware during runtime identifies a code page in memory containing potentially optimizable instructions. The hardware requests allocation of a new page in memory associated with the code page, where the new page contains a collection of counters and each of the counters corresponds to one of the instructions in the code page. When the hardware detects a branch instruction having a branch target within the code page, it increments one of the counters that has the same position in the new page as the branch target in the code page. The execution of the code page is repeated and the counters are incremented when branch targets fall within the code page. The hardware then provides the counter values in the new page to a binary translator for binary translation.