公开(公告)号：WO2013019350A3

公开(公告)日：2013-05-10

申请号：PCT/US2012044805

申请日：2012-06-29

Applicant: INTEL CORP ,  GINZBURG BORIS ,  NATANZON ESFIRUSH ,  OSADCHIY ILYA ,  ZACH YOAV

Inventor： GINZBURG BORIS ,  NATANZON ESFIRUSH ,  OSADCHIY ILYA ,  ZACH YOAV

IPC: G06F9/06 ,  G06F15/163

CPC classification number: G06T1/20 ,  G06T1/60

Abstract: A thread on one processor may be used to enable another processor to lock or release a mutex. For example, a central processing unit thread may be used by a graphics processing unit to secure a mutex for a shared memory.

Abstract translation: 可以使用一个处理器上的线程来使另一个处理器能够锁定或释放互斥体。 例如，图形处理单元可以使用中央处理单元线程来保护用于共享存储器的互斥体。

公开(公告)号：EP2684123A4

公开(公告)日：2014-12-31

申请号：EP11861151

申请日：2011-12-29

Applicant: INTEL CORP

Inventor： GINZBURG BORIS ,  NATANZON ESFIR ,  OSADCHIY ILYA ,  RONEN RONNY ,  WEISSMANN ELIEZER ,  ZACH YOAV ,  FARRELL ROBERT L

IPC: G06F12/10 ,  G06F9/06 ,  G06F9/30 ,  G06F12/08 ,  G06F13/14

CPC classification number: G06F12/1027 ,  G06F12/1036 ,  G06F12/109 ,  G06F2212/302 ,  G06F2212/682

Abstract: Page faults arising in a graphics processing unit may be handled by an operating system running on the central processing unit. In some embodiments, this means that unpinned memory can be used for the graphics processing unit. Using unpinned memory in the graphics processing unit may expand the capabilities of the graphics processing unit in some cases.

Abstract translation: 页面错误在图形处理单元所产生可通过对操作系统运行的中央处理单元上进行处理。 在一些实施方案中，本bedeutet，DASS取消固定存储器可用于图形处理单元。 在图形处理单元，使用未固定的存储器可扩展图形处理单元的在某些情况下的功能。

公开(公告)号：EP2798477A4

公开(公告)日：2015-08-26

申请号：EP11878938

申请日：2011-12-29

Applicant: INTEL CORP

Inventor： RONEN RONNY ,  OSADCHIY ILYA ,  GINZBURG BORIS

IPC: G06F9/30 ,  G06F9/38 ,  G06F11/07 ,  G06F12/08 ,  G06F13/00

CPC classification number: G06F11/0784 ,  G06F9/30036 ,  G06F9/30043 ,  G06F12/08

Abstract: A processor of an aspect includes an instruction pipeline to process a multiple memory address instruction that indicates multiple memory addresses. The processor also includes multiple page fault aggregation logic coupled with the instruction pipeline. The multiple page fault aggregation logic is to aggregate page fault information for multiple page faults that are each associated with one of the multiple memory addresses of the instruction. The multiple page fault aggregation logic is to provide the aggregated page fault information to a page fault communication interface. Other processors, apparatus, methods, and systems are also disclosed.

公开(公告)号：EP2737396A4

公开(公告)日：2015-06-10

申请号：EP12819390

申请日：2012-06-29

Applicant: INTEL CORP

Inventor： GINZBURG BORIS ,  NATANZON ESFIRUSH ,  OSADCHIY ILYA ,  ZACH YOAV

IPC: G06F9/06 ,  G06F15/163

CPC classification number: G06T1/20 ,  G06T1/60

Abstract: A thread on one processor may be used to enable another processor to lock or release a mutex. For example, a central processing unit thread may be used by a graphics processing unit to secure a mutex for a shared memory.

公开(公告)号：EP2686765A4

公开(公告)日：2014-12-31

申请号：EP11861225

申请日：2011-12-29

Applicant: INTEL CORP

Inventor： GINZBURG BORIS ,  NATANZON ESFIRUSH ,  OSADCHIY ILYA ,  RONEN RONNY ,  WEISSMANN ELIEZER ,  ZACH YOAV ,  FARRELL ROBERT L

IPC: G06F9/06 ,  G06F9/22 ,  G06F11/07 ,  G06F12/08

CPC classification number: G06F12/08 ,  G06F2212/302

Abstract: Page faults arising in a graphics processing unit may be handled by an operating system running on the central processing unit. In some embodiments, this means that unpinned memory can be used for the graphics processing unit. Using unpinned memory in the graphics processing unit may expand the capabilities of the graphics processing unit in some cases.