公开(公告)号：DE112015006952T5

公开(公告)日：2018-06-07

申请号：DE112015006952

申请日：2015-10-20

Applicant: INTEL CORP

Inventor： MISHAELI MICHAEL ,  OUZIEL IDO ,  CHAIKIN BARUCH ,  ZACH YOAV

IPC: G06F9/30 ,  G06F9/38

Abstract: Es werden Ausführungsformen von Systemen, Vorrichtungen und Verfahren für die Fernhandlungsabwicklung beschrieben. In einer Ausführungsform umfasst eine Hardware-Vorrichtung Folgendes: ein erstes Register, um eine Speicheradresse von Nutzdaten zu speichern, die einer auszuführenden Handlung entsprechen, die einer Fernhandlungsanforderungsunterbrechung (RAR-Unterbrechung) zugeordnet ist, ein zweites Register, um eine Speicheradresse einer Handlungsliste zu speichern, die durch mehrere Prozessoren zugänglich ist, und eine Fernhandlungs-Handler-Schaltung, um eine empfangene RAR-Unterbrechung zu identifizieren, eine Handlung der empfangenen RAR-Unterbrechung auszuführen und beim Abschluss der Handlung eine Quittung an den einleitenden Prozessor zu signalisieren.

公开(公告)号：WO2013019350A3

公开(公告)日：2013-05-10

申请号：PCT/US2012044805

申请日：2012-06-29

Applicant: INTEL CORP ,  GINZBURG BORIS ,  NATANZON ESFIRUSH ,  OSADCHIY ILYA ,  ZACH YOAV

Inventor： GINZBURG BORIS ,  NATANZON ESFIRUSH ,  OSADCHIY ILYA ,  ZACH YOAV

IPC: G06F9/06 ,  G06F15/163

CPC classification number: G06T1/20 ,  G06T1/60

Abstract: A thread on one processor may be used to enable another processor to lock or release a mutex. For example, a central processing unit thread may be used by a graphics processing unit to secure a mutex for a shared memory.

Abstract translation: 可以使用一个处理器上的线程来使另一个处理器能够锁定或释放互斥体。 例如，图形处理单元可以使用中央处理单元线程来保护用于共享存储器的互斥体。

公开(公告)号：EP2684123A4

公开(公告)日：2014-12-31

申请号：EP11861151

申请日：2011-12-29

Applicant: INTEL CORP

Inventor： GINZBURG BORIS ,  NATANZON ESFIR ,  OSADCHIY ILYA ,  RONEN RONNY ,  WEISSMANN ELIEZER ,  ZACH YOAV ,  FARRELL ROBERT L

IPC: G06F12/10 ,  G06F9/06 ,  G06F9/30 ,  G06F12/08 ,  G06F13/14

CPC classification number: G06F12/1027 ,  G06F12/1036 ,  G06F12/109 ,  G06F2212/302 ,  G06F2212/682

Abstract: Page faults arising in a graphics processing unit may be handled by an operating system running on the central processing unit. In some embodiments, this means that unpinned memory can be used for the graphics processing unit. Using unpinned memory in the graphics processing unit may expand the capabilities of the graphics processing unit in some cases.

Abstract translation: 页面错误在图形处理单元所产生可通过对操作系统运行的中央处理单元上进行处理。 在一些实施方案中，本bedeutet，DASS取消固定存储器可用于图形处理单元。 在图形处理单元，使用未固定的存储器可扩展图形处理单元的在某些情况下的功能。

公开(公告)号：EP2831693A4

公开(公告)日：2015-10-21

申请号：EP12873212

申请日：2012-03-30

Applicant: INTEL CORP

Inventor： WEISSMANN ELIEZER ,  VAITHIANATHAN KARTHIKEYAN KARTHIK ,  ZACH YOAV ,  GINZBURG BORIS ,  RONEN RONNY

IPC: G06F1/00 ,  G06F9/06 ,  G06F9/38 ,  G06F12/10 ,  G06F13/14

CPC classification number: G06F12/0811 ,  G06F3/0646 ,  G06F3/0662 ,  G06F3/0668 ,  G06F9/3851 ,  G06F9/3881 ,  G06F9/3887 ,  G06F12/0292 ,  G06F12/084 ,  G06F12/0875 ,  G06F12/1009 ,  G06F12/1027 ,  G06F12/1045 ,  G06F12/1072 ,  G06F12/1081 ,  G06F12/1441 ,  G06F12/145 ,  G06F2212/1024 ,  G06F2212/283 ,  G06F2212/302 ,  G06F2212/452 ,  G06F2212/60 ,  G06F2212/62 ,  G06F2212/65 ,  G06F2212/68 ,  G06F2212/683 ,  G06F2212/684

Abstract: An apparatus and method are described for coupling a front end core to an accelerator component (e.g., such as a graphics accelerator). For example, an apparatus is described comprising: an accelerator comprising one or more execution units (EUs) to execute a specified set of instructions; and a front end core comprising a translation lookaside buffer (TLB) communicatively coupled to the accelerator and providing memory access services to the accelerator, the memory access services including performing TLB lookup operations to map virtual to physical addresses on behalf of the accelerator and in response to the accelerator requiring access to a system memory.

公开(公告)号：EP2737396A4

公开(公告)日：2015-06-10

申请号：EP12819390

申请日：2012-06-29

Applicant: INTEL CORP

Inventor： GINZBURG BORIS ,  NATANZON ESFIRUSH ,  OSADCHIY ILYA ,  ZACH YOAV

IPC: G06F9/06 ,  G06F15/163

CPC classification number: G06T1/20 ,  G06T1/60

Abstract: A thread on one processor may be used to enable another processor to lock or release a mutex. For example, a central processing unit thread may be used by a graphics processing unit to secure a mutex for a shared memory.

公开(公告)号：EP2686765A4

公开(公告)日：2014-12-31

申请号：EP11861225

申请日：2011-12-29

Applicant: INTEL CORP

Inventor： GINZBURG BORIS ,  NATANZON ESFIRUSH ,  OSADCHIY ILYA ,  RONEN RONNY ,  WEISSMANN ELIEZER ,  ZACH YOAV ,  FARRELL ROBERT L

IPC: G06F9/06 ,  G06F9/22 ,  G06F11/07 ,  G06F12/08

CPC classification number: G06F12/08 ,  G06F2212/302

Abstract: Page faults arising in a graphics processing unit may be handled by an operating system running on the central processing unit. In some embodiments, this means that unpinned memory can be used for the graphics processing unit. Using unpinned memory in the graphics processing unit may expand the capabilities of the graphics processing unit in some cases.