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    APPARATUS AND METHOD OF MASK PERMUTE INSTRUCTIONS
    1.
    发明申请
    APPARATUS AND METHOD OF MASK PERMUTE INSTRUCTIONS 审中-公开
    遮罩说明书的装置和方法

    公开(公告)号：WO2013095613A9

    公开(公告)日：2013-10-10

    申请号：PCT/US2011067090

    申请日：2011-12-23

    Applicant: INTEL CORP ,  OULD-AHMED-VALL ELMOUSTAPHA ,  VALENTINE ROBERT ,  CORBAL JESUS ,  SAIR SULEYMAN

    Inventor： OULD-AHMED-VALL ELMOUSTAPHA ,  VALENTINE ROBERT ,  CORBAL JESUS ,  SAIR SULEYMAN

    IPC: G06F1/00 ,  G06F9/30 ,  G06F9/305

    CPC classification number: G06F9/30032 ,  G06F9/30036 ,  G06F9/30145 ,  G06F15/8092

    Abstract: An apparatus is described having instruction execution logic circuitry. The instruction execution logic circuitry has input vector element routing circuitry to perform the following for each of three different instructions: for each of a plurality of output vector element locations, route into an output vector element location an input vector element from one of a plurality of input vector element locations that are available to source the output vector element. The output vector element and each of the input vector element locations are one of three available bit widths for the three different instructions. The apparatus further includes masking layer circuitry coupled to the input vector element routing circuitry to mask a data structure created by the input vector routing element circuitry. The masking layer circuitry is designed to mask at three different levels of granularity that correspond to the three available bit widths.

    MULTI-ELEMENT INSTRUCTION WITH DIFFERENT READ AND WRITE MASKS
    2.
    发明申请
    MULTI-ELEMENT INSTRUCTION WITH DIFFERENT READ AND WRITE MASKS 审中-公开
    具有不同读取和写入掩码的多元素指令

    公开(公告)号：WO2013095659A1

    公开(公告)日：2013-06-27

    申请号：PCT/US2011067248

    申请日：2011-12-23

    Applicant: INTEL CORP ,  PLOTNIKOV MIKHAIL ,  NARAIKAN ANDREY ,  OULD-AHMED-VALL ELMOUSTAPHA ,  VALENTINE ROBERT ,  TOLL BRET L ,  CORBAL JESUS

    Inventor： PLOTNIKOV MIKHAIL ,  NARAIKAN ANDREY ,  OULD-AHMED-VALL ELMOUSTAPHA ,  VALENTINE ROBERT ,  TOLL BRET L ,  CORBAL JESUS

    IPC: G06F9/30 ,  G06F9/302 ,  G06F9/305

    CPC classification number: G06F9/3013 ,  G06F7/764 ,  G06F9/3001 ,  G06F9/30014 ,  G06F9/30018 ,  G06F9/30029 ,  G06F9/30036

    Abstract: A method is described that includes reading a first read mask from a first register. The method also includes reading a first vector operand from a second register or memory location. The method also includes applying the read mask against the first vector operand to produce a set of elements for operation. The method also includes performing an operation of the set elements. The method also includes creating an output vector by producing multiple instances of the operation's result. The method also includes reading a first write mask from a third register, the first write mask being different than the first read mask. The method also includes applying the write mask against the output vector to create a resultant vector. The method also includes writing the resultant vector to a destination register.

    Abstract translation: 描述了一种包括从第一寄存器读取第一读取掩码的方法。 该方法还包括从第二寄存器或存储器位置读取第一向量操作数。 该方法还包括对第一向量操作数应用读取掩码以产生用于操作的一组元素。 该方法还包括执行设定元件的操作。 该方法还包括通过产生操作结果的多个实例来创建输出向量。 该方法还包括从第三寄存器读取第一写掩码，第一写掩码不同于第一读掩码。 该方法还包括针对输出向量应用写掩码以产生合成矢量。 该方法还包括将结果矢量写入目的地寄存器。

    INSTRUCTION AND LOGIC TO PROVIDE VECTOR LOAD-OP/STORE-OP WITH STRIDE FUNCTIONALITY
    3.
    发明申请
    INSTRUCTION AND LOGIC TO PROVIDE VECTOR LOAD-OP/STORE-OP WITH STRIDE FUNCTIONALITY 审中-公开
    指令和逻辑提供矢量负载/存储 - 功能与功能

    公开(公告)号：WO2013048369A9

    公开(公告)日：2013-10-03

    申请号：PCT/US2011053331

    申请日：2011-09-26

    Applicant: INTEL CORP ,  OULD-AHMED-VALL ELMOUSTAPHA ,  DOSHI KSHITIJ A ,  SAIR SULEYMAN ,  YOUNT CHARLES R

    Inventor： OULD-AHMED-VALL ELMOUSTAPHA ,  DOSHI KSHITIJ A ,  SAIR SULEYMAN ,  YOUNT CHARLES R

    IPC: G06F9/30 ,  G06F9/06 ,  G06F9/305

    CPC classification number: G06F9/30043 ,  G06F9/30018 ,  G06F9/30036 ,  G06F9/3004 ,  G06F9/30101 ,  G06F9/3016 ,  G06F9/30185 ,  G06F9/3455 ,  G06F9/3808 ,  G06F9/3877 ,  G06F9/3887 ,  G06F15/8061

    Abstract: Instructions and logic provide vector load-op and/or store-op with stride functionality. Some embodiments, responsive to an instruction specifying: a set of loads, a second operation, destination register, operand register, memory address, and stride length; execution units read values in a mask register, wherein fields in the mask register correspond to stride-length multiples from the memory address to data elements in memory. A first mask value indicates the element has not been loaded from memory and a second value indicates that the element does not need to be, or has already been loaded. For each having the first value, the data element is loaded from memory into the corresponding destination register location, and the corresponding value in the mask register is changed to the second value. Then the second operation is performed using corresponding data in the destination and operand registers to generate results. The instruction may be restarted after faults.

    Abstract translation: 指令和逻辑提供矢量加载操作和/或存储操作与步幅功能。 一些实施例，响应于指令：一组负载，第二操作，目的地寄存器，操作数寄存器，存储器地址和步幅长度; 执行单元读取掩码寄存器中的值，其中掩码寄存器中的字段对应于从存储器地址到存储器中的数据元素的跨距长度倍数。 第一个掩码值表示元素尚未从内存中加载，第二个值表示元素不需要或已经被加载。 对于具有第一个值的每一个，数据元素从存储器加载到相应的目标寄存器位置，并且掩码寄存器中的对应值被改变为第二值。 然后使用目的地和操作数寄存器中的相应数据执行第二个操作，以生成结果。 指令可能在故障后重新启动。

    INSTRUCTION AND LOGIC TO PROVIDE VECTOR LOADS AND STORES WITH STRIDES AND MASKING FUNCTIONALITY
    4.
    发明申请
    INSTRUCTION AND LOGIC TO PROVIDE VECTOR LOADS AND STORES WITH STRIDES AND MASKING FUNCTIONALITY 审中-公开
    指令和逻辑提供矢量负载和存储带有条件和屏蔽功能

    公开(公告)号：WO2013048367A9

    公开(公告)日：2013-11-14

    申请号：PCT/US2011053321

    申请日：2011-09-26

    Applicant: INTEL CORP ,  OULD-AHMED-VALL ELMOUSTAPHA ,  DOSHI KSHITIJ A ,  SAIR SULEYMAN ,  YOUNT CHARLES R

    Inventor： OULD-AHMED-VALL ELMOUSTAPHA ,  DOSHI KSHITIJ A ,  SAIR SULEYMAN ,  YOUNT CHARLES R

    IPC: G06F9/30 ,  G06F9/06 ,  G06F9/305

    CPC classification number: G06F9/30043 ,  G06F9/30018 ,  G06F9/30036 ,  G06F9/30101 ,  G06F9/3455

    Abstract: Instructions and logic provide vector loads and/or stores with stride and mask functionality. Some embodiments, responsive to an instruction specifying: a set of loads, destination register, mask register, memory address, and stride length; execution units read values in the mask register, wherein fields in the mask register correspond to stride-length multiples from the memory address to data elements in memory. A first mask value indicates the element has not been loaded from memory and a second value indicates that the element does not need to be, or has already been loaded. For each having the first value, the corresponding multiple of said stride length is generated according to the data field's position in the mask register to load the data element from memory into the corresponding destination register location, and the corresponding value in the mask register is changed to the second value. These instructions can restart after faults.

    Abstract translation: 指令和逻辑提供带有步幅和掩码功能的向量加载和/或存储。 一些实施例，响应于指令：一组负载，目的地寄存器，掩码寄存器，存储器地址和步幅长度; 执行单元读取掩码寄存器中的值，其中掩码寄存器中的字段对应于从存储器地址到存储器中的数据元素的跨距长度倍数。 第一个掩码值表示元素尚未从内存加载，第二个值表示该元素不需要或已经被加载。 对于具有第一值的每一个，根据数据字段在屏蔽寄存器中的位置产生所述步幅长度的对应倍数，以将数据元素从存储器加载到相应的目的地寄存器位置，并且屏蔽寄存器中的对应值被改变 到第二个值。 这些说明可以在故障后重新启动。

    DOT PRODUCT PROCESSORS, METHODS, SYSTEMS, AND INSTRUCTIONS
    7.
    发明公开
    DOT PRODUCT PROCESSORS, METHODS, SYSTEMS, AND INSTRUCTIONS 审中-公开
    SKALARPRODUKTPROZESSOREN SOWIE VERFAHREN，SYSTEME UND ANWEISUNGENDAFÜR

    公开(公告)号：EP2798457A4

    公开(公告)日：2016-07-27

    申请号：EP11878520

    申请日：2011-12-29

    Applicant: INTEL CORP

    Inventor： KRISHNAN KARTHIKEYAN ,  OULD-AHMED-VALL ELMOUSTAPHA ,  CHEREPANOV VICTOR

    IPC: G06F9/06 ,  G06F7/48 ,  G06F9/30 ,  G06F13/14

    CPC classification number: G06F9/3001 ,  G06F7/5443 ,  G06F9/30014 ,  G06F9/30036 ,  G06F9/30109 ,  G06F9/30192

    Abstract: A method of an aspect includes receiving a dot product instruction. The dot product instruction indicates a first source packed data including at least four data elements, indicates a second source packed data including at least eight data elements, and indicates a destination storage location. A result packed data is stored in the destination storage location in response to the dot product instruction. The result includes a plurality of data elements that each includes a dot product result. Each of the dot product results includes a sum of products of the at least four data elements of the first source packed data with corresponding data elements in a different subset of at least four data elements of the second source packed data. Other methods, apparatus, systems, and instructions are disclosed.

    Abstract translation: 一方面的方法包括接收点积指令。 点产品指令指示包括至少四个数据元素的第一源打包数据，指示包括至少八个数据元素的第二源打包数据，并且指示目的地存储位置。 响应于点积指令，结果打包数据被存储在目的地存储位置。 结果包括多个数据元素，每个数据元素包括点积结果。 每个点积结果包括第一源打包数据的至少四个数据元素与第二源打包数据的至少四个数据元素的不同子集中的对应数据元素的乘积之和。 公开了其它方法，装置，系统和指令。

    APPARATUS AND METHOD TO REVERSE AND PERMUTE BITS IN A MASK REGISTER
    9.
    发明公开
    APPARATUS AND METHOD TO REVERSE AND PERMUTE BITS IN A MASK REGISTER 审中-公开
    VORRICHTUNG UND VERFAHREN ZUR REVERSIERUNG UND PERMUTIERUNG VON位于EINEM MASKENREGISTER

    公开(公告)号：EP3014417A4

    公开(公告)日：2017-06-21

    申请号：EP14817656

    申请日：2014-06-17

    Applicant: INTEL CORP

    Inventor： OULD-AHMED-VALL ELMOUSTAPHA ,  VALENTINE ROBERT

    IPC: G06F9/06 ,  G06F9/30

    CPC classification number: G06F9/30018 ,  G06F9/30032 ,  G06F9/30036 ,  G06F9/30098

    Abstract: An apparatus and method are described for performing a bit reversal and permutation on mask values. For example, a processor is described to execute an instruction to perform the operations of: reading a plurality of mask bits stored in a source mask register, the mask bits associated with vector data elements of a vector register; and performing a bit reversal operation to copy each mask bit from a source mask register to a destination mask register, wherein the bit reversal operation causes bits from the source mask register to be reversed within the destination mask register resulting in a symmetric, mirror image of the original bit arrangement.

    Abstract translation: 描述了用于对掩码值执行位反转和置换的设备和方法。 例如，处理器被描述为执行指令以执行以下操作：读取存储在源掩码寄存器中的多个掩码比特，掩码比特与矢量寄存器的矢量数据元素相关联; 以及执行位反转操作以将每个屏蔽位从源屏蔽寄存器复制到目的地屏蔽寄存器，其中所述位反转操作使得来自所述源屏蔽寄存器的位在所述目的地屏蔽寄存器内反转，导致对称的镜像 原来的位排列。

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