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    APPARATUS AND METHOD OF MASK PERMUTE INSTRUCTIONS
    4.
    发明申请
    APPARATUS AND METHOD OF MASK PERMUTE INSTRUCTIONS 审中-公开
    遮罩说明书的装置和方法

    公开(公告)号：WO2013095613A9

    公开(公告)日：2013-10-10

    申请号：PCT/US2011067090

    申请日：2011-12-23

    Applicant: INTEL CORP ,  OULD-AHMED-VALL ELMOUSTAPHA ,  VALENTINE ROBERT ,  CORBAL JESUS ,  SAIR SULEYMAN

    Inventor： OULD-AHMED-VALL ELMOUSTAPHA ,  VALENTINE ROBERT ,  CORBAL JESUS ,  SAIR SULEYMAN

    IPC: G06F1/00 ,  G06F9/30 ,  G06F9/305

    CPC classification number: G06F9/30032 ,  G06F9/30036 ,  G06F9/30145 ,  G06F15/8092

    Abstract: An apparatus is described having instruction execution logic circuitry. The instruction execution logic circuitry has input vector element routing circuitry to perform the following for each of three different instructions: for each of a plurality of output vector element locations, route into an output vector element location an input vector element from one of a plurality of input vector element locations that are available to source the output vector element. The output vector element and each of the input vector element locations are one of three available bit widths for the three different instructions. The apparatus further includes masking layer circuitry coupled to the input vector element routing circuitry to mask a data structure created by the input vector routing element circuitry. The masking layer circuitry is designed to mask at three different levels of granularity that correspond to the three available bit widths.

    MULTI-ELEMENT INSTRUCTION WITH DIFFERENT READ AND WRITE MASKS
    5.
    发明申请
    MULTI-ELEMENT INSTRUCTION WITH DIFFERENT READ AND WRITE MASKS 审中-公开
    具有不同读取和写入掩码的多元素指令

    公开(公告)号：WO2013095659A1

    公开(公告)日：2013-06-27

    申请号：PCT/US2011067248

    申请日：2011-12-23

    Applicant: INTEL CORP ,  PLOTNIKOV MIKHAIL ,  NARAIKAN ANDREY ,  OULD-AHMED-VALL ELMOUSTAPHA ,  VALENTINE ROBERT ,  TOLL BRET L ,  CORBAL JESUS

    Inventor： PLOTNIKOV MIKHAIL ,  NARAIKAN ANDREY ,  OULD-AHMED-VALL ELMOUSTAPHA ,  VALENTINE ROBERT ,  TOLL BRET L ,  CORBAL JESUS

    IPC: G06F9/30 ,  G06F9/302 ,  G06F9/305

    CPC classification number: G06F9/3013 ,  G06F7/764 ,  G06F9/3001 ,  G06F9/30014 ,  G06F9/30018 ,  G06F9/30029 ,  G06F9/30036

    Abstract: A method is described that includes reading a first read mask from a first register. The method also includes reading a first vector operand from a second register or memory location. The method also includes applying the read mask against the first vector operand to produce a set of elements for operation. The method also includes performing an operation of the set elements. The method also includes creating an output vector by producing multiple instances of the operation's result. The method also includes reading a first write mask from a third register, the first write mask being different than the first read mask. The method also includes applying the write mask against the output vector to create a resultant vector. The method also includes writing the resultant vector to a destination register.

    Abstract translation: 描述了一种包括从第一寄存器读取第一读取掩码的方法。 该方法还包括从第二寄存器或存储器位置读取第一向量操作数。 该方法还包括对第一向量操作数应用读取掩码以产生用于操作的一组元素。 该方法还包括执行设定元件的操作。 该方法还包括通过产生操作结果的多个实例来创建输出向量。 该方法还包括从第三寄存器读取第一写掩码，第一写掩码不同于第一读掩码。 该方法还包括针对输出向量应用写掩码以产生合成矢量。 该方法还包括将结果矢量写入目的地寄存器。

    LOCALIZED PERFORMANCE THROTTLING TO REDUCE IC POWER CONSUMPTION
    9.
    发明公开
    LOCALIZED PERFORMANCE THROTTLING TO REDUCE IC POWER CONSUMPTION 失效
    当地的电力控制来降低集成电路的能耗

    公开(公告)号：EP1023656A4

    公开(公告)日：2002-07-03

    申请号：EP97944556

    申请日：1997-09-29

    Applicant: INTEL CORP

    Inventor： MITTAL MILLIND ,  VALENTINE ROBERT

    IPC: G06F1/32

    CPC classification number: G06F9/3842 ,  G06F1/32 ,  G06F9/3001 ,  G06F9/3802 ,  G06F9/3836 ,  G06F9/3857

    Abstract: The power consumed within an integrated circuit (IC) is reduced by throttling the performance of particular functional units (105) within the IC. The recent utilization levels of particular functional units within an IC are monitored (108), for example, by computing each functional unit's average duty cycle over its recent operating history (106). If this activity level (109) is greater than a threshold, the functional unit is operated in a reduced-power mode (110). The threshold value is set large enough to allow short bursts of high utilization to occur. An IC can dynamically make the tradeoff between high-speed operation and low-power operation, by throttling back performance of functional units when their utilization exceeds a sustainable level. This dynamic power/speed tradeoff can be optimized across multiple functional units within an IC or among multiple ICs within a system. This dynamic power/speed tradeoff can be altered by providing software control over throttling parameters.

    METHOD AND APPARATUS FOR VECTOR INDEX LOAD AND STORE
    10.
    发明公开
    METHOD AND APPARATUS FOR VECTOR INDEX LOAD AND STORE 审中-公开

    公开(公告)号：EP3238026A4

    公开(公告)日：2018-08-01

    申请号：EP15873962

    申请日：2015-11-23

    Applicant: INTEL CORP

    Inventor： JHA ASHISH ,  VALENTINE ROBERT ,  OULD-AHMED-VALL ELMOUSTAPHA

    IPC: G06F9/30 ,  G06F12/02

    CPC classification number: G06F9/30036 ,  G06F9/30018 ,  G06F9/30043 ,  G06F9/30101 ,  G06F15/8053

    Abstract: An apparatus and method for performing vector index loads and stores. For example, one embodiment of a processor comprises: a vector index register to store a plurality of index values; a mask register to store a plurality of mask bits; a vector register to store a plurality of vector data elements loaded from memory; and vector index load logic to identify an index stored in the vector index register to be used for a load operation using an immediate value and to responsively combine the index with a base memory address to determine a memory address for the load operation, the vector index load logic to load vector data elements from the memory address to the vector register in accordance with the plurality of mask bits.

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