公开(公告)号：EP2792027A4

公开(公告)日：2015-09-09

申请号：EP11877554

申请日：2011-12-14

Applicant: INTEL CORP

Inventor： JAUSSI JAMES E ,  MOONEY STEPHEN R ,  HECK HOWARD L ,  PEDERSON BRUCE E ,  CASPER BRYAN K

IPC: H01R12/71 ,  H01R12/72 ,  H01R13/629 ,  H01R13/66 ,  H01R24/62

CPC classification number: H01R24/64 ,  H01R12/721 ,  H01R13/66 ,  H01R13/6658 ,  H01R24/28 ,  H01R24/62 ,  H01R2107/00

Abstract: Methods and systems may include an input/output (IO) interface that has an integrated buffer, a housing and a substrate disposed within the housing. The substrate may include a first side, a second side and a connection edge. The integrated buffer can be coupled to at least one of the first side and the second side of the substrate. A plurality of rows of contacts may be coupled to the first side of the substrate. Each row of contacts can be stacked substantially parallel to the connection edge. The substrate may have power outputs coupled thereto and the integrated buffer can include a voltage regulator that has a supply output coupled to the power outputs.

Abstract translation: 方法和系统可以包括具有集成缓冲器，壳体和布置在壳体内的基板的输入/输出（IO）接口。 衬底可以包括第一侧，第二侧和连接边缘。 集成缓冲器可以耦合到衬底的第一侧面和第二侧面中的至少一个。 多个触点列可以耦合到衬底的第一侧。 每排触点可以基本上平行于连接边缘堆叠。 衬底可以具有耦合到其上的功率输出，并且集成缓冲器可以包括具有耦合到功率输出的电源输出的电压调节器。