ELECTRICAL INTERCONNECT FOR AN ELECTRONIC PACKAGE

    公开(公告)号:MY175102A

    公开(公告)日:2020-06-06

    申请号:MYPI2015703725

    申请日:2015-10-16

    Applicant: INTEL CORP

    Abstract: Some example forms relate to an electrical interconnect (10, 70) for an electronic package (30A, 30B, 90). The electrical interconnect (10, 70) includes a dielectric layer (11, 71) that includes a trench (12, 75) formed into one surface of the dielectric layer (11, 71) and a signal conductor (14, 76) that fills the trench (12, 75) and extends above the one surface of dielectric layer (11, 71). The electrical interconnect (10, 70) further includes a conductive reference layer (15, 77) mounted on an opposing side of the dielectric layer (11, 71). The conductive reference layer (15, 77) is electromagnetically coupled to the signal conductor (14, 76) when current passes through the signal conductor (14, 76).

    Verfahren und Vorrichtung zur USB-3.1-Retimer-Präsenzdetektion und Indexierung

    公开(公告)号:DE112015003041T5

    公开(公告)日:2017-04-20

    申请号:DE112015003041

    申请日:2015-05-27

    Applicant: INTEL CORP

    Abstract: Eine Vorrichtung zur Retimer-Präsenzdetektion wird hierin beschrieben. Die Vorrichtung umfasst wenigstens einen Retimer, wobei ein Algorithmus ermöglichen soll, dass der wenigstens eine Retimer seine Präsenz ankündigt, indem ein Bit einer Präsenznachricht während der Link-Initialisierung assertiert wird. Der wenigstens eine Retimer kann einen Index deklarieren und ist über den Index zugänglich.

    METHOD AND APPARATUS OF USB 3.1 RETIMER PRESENCE DETECT AND INDEX

    公开(公告)号:SG11201609921VA

    公开(公告)日:2016-12-29

    申请号:SG11201609921V

    申请日:2015-05-27

    Applicant: INTEL CORP

    Abstract: An apparatus for retimer presence detection is described herein. The apparatus includes at least one retimer, wherein an algorithm is to enable the at least one retimer to announce its presence by asserting a bit of a presence message during link initialization. The at least one retimer can declare an index and is accessible via the index.

    RE-DRIVER POWER MANAGEMENT
    6.
    发明公开
    RE-DRIVER POWER MANAGEMENT 审中-公开
    LEISTUNGSVERWALTUNG EINES REDRIVERS

    公开(公告)号:EP2936267A4

    公开(公告)日:2016-08-03

    申请号:EP13865454

    申请日:2013-12-11

    Applicant: INTEL CORP

    Abstract: The present disclosure provides techniques for increasing the power efficiency of re-drivers by providing a technique for a re-driver to recognize a variety of power states. A message generator may be located in a host device and may encode a signal indicating a change in a power state. The message may be transmitted to a message decoder located in a re-driver. The message decoder may decode the message and the re-driver may enter a power state in response to the decoded message.

    Abstract translation: 本公开提供了通过提供用于重新驱动程序识别各种功率状态的技术来提高重新驱动器的功率效率的技术。 消息发生器可以位于主机设备中,并且可以编码指示功率状态改变的信号。 消息可以被发送到位于重新驱动器中的消息解码器。 消息解码器可以对消息进行解码,并且重新驱动器可以响应于解码的消息而进入功率状态。

    RATE SCALABLE CONNECTOR FOR HIGH BANDWIDTH CONSUMER APPLICATIONS
    7.
    发明公开
    RATE SCALABLE CONNECTOR FOR HIGH BANDWIDTH CONSUMER APPLICATIONS 审中-公开
    VERBINDER MIT SKALIERBARER RATEFÜRVERBRAUCHERANWENDUNGEN MIT HOHER BANDBREITE

    公开(公告)号:EP2792027A4

    公开(公告)日:2015-09-09

    申请号:EP11877554

    申请日:2011-12-14

    Applicant: INTEL CORP

    Abstract: Methods and systems may include an input/output (IO) interface that has an integrated buffer, a housing and a substrate disposed within the housing. The substrate may include a first side, a second side and a connection edge. The integrated buffer can be coupled to at least one of the first side and the second side of the substrate. A plurality of rows of contacts may be coupled to the first side of the substrate. Each row of contacts can be stacked substantially parallel to the connection edge. The substrate may have power outputs coupled thereto and the integrated buffer can include a voltage regulator that has a supply output coupled to the power outputs.

    Abstract translation: 方法和系统可以包括具有集成缓冲器,壳体和布置在壳体内的基板的输入/输出(IO)接口。 衬底可以包括第一侧,第二侧和连接边缘。 集成缓冲器可以耦合到衬底的第一侧面和第二侧面中的至少一个。 多个触点列可以耦合到衬底的第一侧。 每排触点可以基本上平行于连接边缘堆叠。 衬底可以具有耦合到其上的功率输出,并且集成缓冲器可以包括具有耦合到功率输出的电源输出的电压调节器。

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