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    Verfahren und Einrichtung zum Regeln der Temperatur eines Bauelements
    1.
    发明专利
    Verfahren und Einrichtung zum Regeln der Temperatur eines Bauelements 未知

    公开(公告)号：DE19983470B4

    公开(公告)日：2011-08-18

    申请号：DE19983470

    申请日：1999-08-13

    Applicant: INTEL CORP

    Inventor： JAIN SATCHITANAND ,  REINHARDT DENNIS ,  CHO SUNG-SOO

    IPC: G11C7/04 ,  G11C7/00 ,  G11C7/22 ,  G11C11/406 ,  G11C11/407

    Abstract: Eine Einrichtung zum Regeln der Temperatur eines Bauelements, aufweisend: eine Steuereinrichtung, die mit dem Bauelement derart koppelbar ist, dass sie ein für die Temperatur des Bauelements repräsentatives Temperatursignal empfängt, wobei die Steuereinrichtung so ausgebildet ist, daß sie eine Übertragungsrate der von der Steuereinrichtung zu dem Bauelement übertragenen Daten und/oder der von dem Bauelement an der Steuereinrichtung angenommenen Daten in Abhängigkeit von der Temperatur des Bauelements steuert, wobei die Steuerung derart erfolgt, dass die Übertragungsrate bei einer höheren Temperatur geringer ist als bei einer niedrigeren Temperatur.

    Method and apparatus to control the temperature of a component
    4.
    发明专利
    Method and apparatus to control the temperature of a component 未知

    公开(公告)号：GB2358944A

    公开(公告)日：2001-08-08

    申请号：GB0103092

    申请日：1999-08-13

    Applicant: INTEL CORP

    Inventor： JAIN SATCHITANAND ,  REINHARDT DENNIS ,  CHO SUNG-SOO

    IPC: G11C7/04 ,  G11C7/22 ,  G11C11/406 ,  G11C7/00

    Abstract: When a component, such as a memory device, exhibits an overtemperature condition (e.g., exceeds a first threshold value), the data transmission rate with respect to the component is reduced so as to lower its operating temperature. In one embodiment, this is achieved by changing the latency at which data packets are transmitted to and from the memory device in dependance on the temperature of the device. Controlling temperature in such a fashion allows for efficient use of the component over a large range of temperatures.

    Method and apparatus for caching system management mode information with other information
    7.
    发明专利
    Method and apparatus for caching system management mode information with other information 未知

    公开(公告)号：AU3297597A

    公开(公告)日：1998-01-05

    申请号：AU3297597

    申请日：1997-05-27

    Applicant: INTEL CORP

    Inventor： REINHARDT DENNIS ,  KARDACH JAMES P ,  HORIGAN JOHN W ,  SONGER NEIL ,  GLEW ANDREW F

    IPC: G06F9/48 ,  G06F12/02 ,  G06F12/06 ,  G06F12/08 ,  G06F12/14 ,  G06F9/30 ,  G06F9/22 ,  G06F12/10

    Abstract: A novel method and apparatus to cache System Management Mode (SMM) data with other data to improve performance and reduce latency of SMM handler routines. This method and apparatus allows SMM data and non-SMM data to be distinguished in the cache without requiring extra cache bits which can add to the cost of implementation. Since SMM data and non-SMM data can coexist in the cache, there is no need for time consuming cache flush cycles when switching between the two modes. Since SMM data can be cached, performance of SMM routines are improved. This method and apparatus defines the SMRAM address range to be a range of addresses representable by the tag, but not directly corresponding to installed main memory. When accesses are made to SMRAM addresses, they are redirected to an unused portion of main memory. Protection mechanisms may be implemented to limit access to these SMRAM addresses when not in SMM.

    8.
    发明专利
    未知

    公开(公告)号：DE69732181D1

    公开(公告)日：2005-02-10

    申请号：DE69732181

    申请日：1997-05-27

    Applicant: INTEL CORP

    Inventor： REINHARDT DENNIS ,  KARDACH P ,  HORIGAN W ,  SONGER NEIL ,  GLEW F

    IPC: G06F9/48 ,  G06F12/02 ,  G06F12/06 ,  G06F12/08 ,  G06F12/14 ,  G06F9/30 ,  G06F9/22 ,  G06F12/10 ,  G06F9/46

    Abstract: A novel method and apparatus to cache System Management Mode (SMM) data with other data to improve performance and reduce latency of SMM handler routines. This method and apparatus allows SMM data and non-SMM data to be distinguished in the cache without requiring extra cache bits which can add to the cost of implementation. Since SMM data and non-SMM data can coexist in the cache, there is no need for time consuming cache flush cycles when switching between the two modes. Since SMM data can be cached, performance of SMM routines are improved. This method and apparatus defines the SMRAM address range to be a range of addresses representable by the tag, but not directly corresponding to installed main memory. When accesses are made to SMRAM addresses, they are redirected to an unused portion of main memory. Protection mechanisms may be implemented to limit access to these SMRAM addresses when not in SMM.

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